Date : Thu, 05 May 1988 04:13:30 GMT
From : osu-cis!n8emr!oink!jep@tut.cis.ohio-state.edu (James E. Prior)
Subject: Godbout RAM 23 PAL equations
At the end of this article are the PAL equations for upgrading a
64K RAM 23 board to 128K.
Years ago, I bought a half populated RAM 23 board. i.e. 64K out of 128K.
If you added more RAM chips, you had to change the PAL. The 128K PAL would
work fine with a half populated board, but a 64K PAL wouldn't work with more
than 64K of RAM.
This was Godbout's way of screwing over customers. It really teed me off.
They had to go OUT OF THEIR WAY to put a restricted PAL in the half populated
boards. Keep in mind that a 64K PAL and my 128K PAL start out as the same
chip, they are just burnt different. Their 64K PAL does cute things like
turning on several banks of chips when you try to access something over 64K.
This has the tendancy to burn up the output drivers of your RAM chips.
I had previously liked the openness and versatility of S-100 hardware,
Godbout's
in particular. I was considering recommending their stuff for use in test
rigs. After my experience with the 64K RAM 23 board, I haven't felt
comfortable enough to do so.
I have never forgotten about the arrogant, malicious attitude shown by their
intention bad design.
I've never seen a fully populated board from Godbout, but I knew that the
PAL had to be simple, so I figured out what I'd like the PAL to do, and wrote
the equations. It was a fun exercise in that respect. My PAL worked
on the first try. It works fine with either a half populated or a fully
populated board.
One note of caution, the original PAL allowed writes to RAM while phantom is
asserted, violating the IEEE-696 spec:
2.2.9.6 Phantom Slaves (PHANTOM*). A
line, PHANTOM*, is provided for overlaying
memory slaves at a common address location.
When this line is activated phantom memory
slaves are enabled and normal memory slaves
are disabled. All normal memory slaves shall
have the capability of being disabled in response
to PHANTOM*. Memory slaves shall be disabled
during PHANTOM* for both read and write cycles.
This line is specified as an open-collector line.
Note the explicit proscription against writes during PHANTOM*.
Godbout's CP/M 68K relies upon using RAM boards that violate IEEE-696
by writing to RAM while PHANTOM* is asserted. I never found any documentation
of their's that mentioned this violation of IEEE-696. I had to figure it
out the hard way when I put in non-Godbout boards that followed IEEE-696
by disabling writes while PHANTOM* is asserted.
I have intentionally implemented the same violation, so that I can boot
CP/M 68K. I think being able to write during PHANTOM* is a desirable
thing to have in the spec, but it is damnable of Godbout to claim adherance
to the IEEE-696 spec, when such a violation has been implemented without
even so much as a notice that they did it. They should have put another
jumper to select whether you want to enable of disable writes during
PHANTOM*. The PAL has spare input pins to implement such an option.
The PAL goes in socket U7.
I've had my PAL in use for quite some time now. I didn't think to post
the equations until a friend recently asked for them. I hope this helps
those of you with 64K RAM 23 boards.
title Address decoder for 128K Viasyn RAM 23 board
pattern godbout.pds
revision a
author James Prior
company No
date 86/03/01
chip godbout pal16l8
nc nc /sWO sMEMR /PHANT /sXTRQ sOUT A16S A15 gnd
A0 /cs1b0 /cs1a0 /cs1b1 /cs1b2 /cs1b3 /cs1a3 /cs1a2 /cs1a1 vcc
equations
cs1a0 = /PHANT * sMEMR * /sWO * /sOUT * sXTRQ * /A16S * /A15
+ /sMEMR * sWO * /sOUT * sXTRQ * /A16S * /A15
+ /PHANT * sMEMR * /sWO * /sOUT * /A0 * /A16S * /A15
+ /sMEMR * sWO * /sOUT * /A0 * /A16S * /A15
cs1a1 = /PHANT * sMEMR * /sWO * /sOUT * sXTRQ * /A16S * A15
+ /sMEMR * sWO * /sOUT * sXTRQ * /A16S * A15
+ /PHANT * sMEMR * /sWO * /sOUT * /A0 * /A16S * A15
+ /sMEMR * sWO * /sOUT * /A0 * /A16S * A15
cs1a2 = /PHANT * sMEMR * /sWO * /sOUT * sXTRQ * A16S * /A15
+ /sMEMR * sWO * /sOUT * sXTRQ * A16S * /A15
+ /PHANT * sMEMR * /sWO * /sOUT * /A0 * A16S * /A15
+ /sMEMR * sWO * /sOUT * /A0 * A16S * /A15
cs1a3 = /PHANT * sMEMR * /sWO * /sOUT * sXTRQ * A16S * A15
+ /sMEMR * sWO * /sOUT * sXTRQ * A16S * A15
+ /PHANT * sMEMR * /sWO * /sOUT * /A0 * A16S * A15
+ /sMEMR * sWO * /sOUT * /A0 * A16S * A15
cs1b0 = /PHANT * sMEMR * /sWO * /sOUT * sXTRQ * /A16S * /A15
+ /sMEMR * sWO * /sOUT * sXTRQ * /A16S * /A15
+ /PHANT * sMEMR * /sWO * /sOUT * A0 * /A16S * /A15
+ /sMEMR * sWO * /sOUT * A0 * /A16S * /A15
cs1b1 = /PHANT * sMEMR * /sWO * /sOUT * sXTRQ * /A16S * A15
+ /sMEMR * sWO * /sOUT * sXTRQ * /A16S * A15
+ /PHANT * sMEMR * /sWO * /sOUT * A0 * /A16S * A15
+ /sMEMR * sWO * /sOUT * A0 * /A16S * A15
cs1b2 = /PHANT * sMEMR * /sWO * /sOUT * sXTRQ * A16S * /A15
+ /sMEMR * sWO * /sOUT * sXTRQ * A16S * /A15
+ /PHANT * sMEMR * /sWO * /sOUT * A0 * A16S * /A15
+ /sMEMR * sWO * /sOUT * A0 * A16S * /A15
cs1b3 = /PHANT * sMEMR * /sWO * /sOUT * sXTRQ * A16S * A15
+ /sMEMR * sWO * /sOUT * sXTRQ * A16S * A15
+ /PHANT * sMEMR * /sWO * /sOUT * A0 * A16S * A15
+ /sMEMR * sWO * /sOUT * A0 * A16S * A15
;description:
;
;nc nc /sWO sMEMR /PHANT sXTRQ sOUT A16S A15 gnd
;A0 /cs1b0 /cs1a0 /cs1b1 /cs1b2 /cs1b3 /cs1a3 /cs1a2 /cs1a1 vcc
;
; 0 i/o p Name Description
;
; 1 i ground useless pin
; 2 i ground useless pin
; 3 i sWO* write cycle status straight from
S-100 bus
; 4 i sMEMR memory read cycle status straight from
S-100 bus
; 5 i PHANT* phantom when asserted disables RAM
; reads to allow reading of boot ROM straight from
S-100 bus
; 6 i sXTRQ* 16 bit transfer status straight from
S-100 bus
; 7 i sOUT output cycle status straight from
S-100 bus
; 8 i A16S ground if 64K board
; A16 if 128K board straight from
S-100 bus
; 9 i A15 A15 straight from
S-100 bus
;10 ground
;
;11 i A0 A0, chooses between
;12 o cs1b0*
;13 o cs1a0*
;14 o cs1b1*
;15 o cs1b2*
;16 o cs1b3*
;17 o cs1a3*
;18 o cs1a2*
;19 o cs1a1*
;20 Vcc +5V power
--
Jim Prior {ihnp4|osu-cis}!n8emr!oink!jep jep@oink.UUCP
Pointers are my friend.