Date   : Sun, 15 May 1988 20:39:22 GMT
From   : pilchuck!del@uunet.uu.net (Erik Lindberg)
Subject: Ithaca Intersystems 256KDR S-100 memory

In article <1481*kenw@noah.arc.cdn> kenw%noah.arc.CDN@ean.ubc.ca (Ken Wallewein)
writes:
>
>  I have a couple of Ithaca Intersystems 256KDR S-100 memory boards which I'd 
>really like to use. 512 kb would be rather nice, and there's more where they 
>came from. 
>

Oh yeah? How can *I* get some?

>keep some memory common, to execute in, won't it? The only thing I can think
>of is to hack up the board, moving the boards address bits 16 through 23 down
>one where they connect to the bus, putting them on 15 through 22, and tying
>the internal bit 15 low (I think). That would make everything show up in the
>low 32k only. 
>  
>     Surely there's a better way...? 
>

You could do what I did. A little awkward, but the results were quite nice.
Using a wire wrap board that allows orientation of a socket with no
restrictions, place a 40 pin three level W/W socket such that it's pins
can be inserted into the CPU board Z80 socket, sandwich style. Also place
the TI MMU chip (it's a 40 pin chip, 7461x series) on the board somewhere.
Put the Z80 on another W/W socket real close to the main CPU socket, and
connect all same-numbered pins together, except the ones that need to be
interrupted to the MMU chip. A little bit of decode logic and you're in
business: A two board CPU sandwich that allows you to map any 4k block
in 24 bit space to any 4k block in 16 bit space.

In the interest of simplicity, I recommend that you do not attempt to
implement the register read features of the chip. It will conflict with the
on board buffers of the main CPU and cause you no end of grief if you try.

Also, since the data bus of the mapping chip during map register access is
also the address bus input, I found that rather than buffering and steering
the data bus it was far easier to just program the chip through the address
bus of the Z80. It is a seldom used feature of the Z80, but you can write
to a port while generating an 8 bit port address on the low byte of the 
address bus, while putting another register on the high byte of the address
bus. That register will be either the "A" or the "B" register, depending on
which output instruction you are using.

I have actually implemented this kludge on the Computime Z80 CPU board. I got
carried away and put a DMA chip and SCSI interface on the W/W board, 
since it bugged me to see all that wasted real-estate. Unfortunately, the
added capacitive loading of the extra chips and wiring made the system
unreliable at 6Mhz, and I had to throttle back to 4Mhz. Grumble. In
retrospect, board real-estate is cheap ($35) I would have been better off
just using two W/W boards.

-- 
del (Erik Lindberg) 
uw-beaver!tikal!pilchuck!del


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