Date   : Thu, 02 Jul 1992 08:48:16 -0500
From   : curts@tmpcu.mdc.com (Curt Schroeder)
Subject: Apple II CP/M with an accelerated 65c02

I have one of the 8MHz ZIP chip 65c02 CPUs in my trusty II+ (talk about
breathing new life into the machine 8-) 

Unfortunately, if you are using a Microsoft compatible Z80 board (mine is from
Nexco, now known as Price-Busters I think) you can not take advantage of the
ZIP chip.  Why?  Well, a Microsoft Compatible Z80 board uses DMA to access the
system memory.  Since, it is using DMA, it is changing memory addresses without
updating the tags in the ZIP chip's 8K cache.  So when the 65c02 kicks in to
do I/O operations for the Z80, it is ignorant of many changes to memory.  The
bottom line is that CP/M wont even boot with the acceleration enabled.

I have toyed with the notion of upgrading my graphics package to draw an
entire polyline (multiple line segments) at once on the 6502 side so that I
could pass the data list pointer and length to the 6502, update the cache,
enable acceleration, draw all the line segments in the polyline, disable
acceleration, and pass control back to the Z80.  Currenlty I draw only one
line segment at a time, so  you have the overhead of switching to the 6502
and back to the Z80 each time.  Its not too bad for lines, but making
individual pixel calls is SLOW this way.  But it works!

I wish someone would do a Z80 replacement with on-chip cache memory for
accelerated execution!  The 65c02 one is fantastic to have!

Curt

Curt Schroeder | McDonnell Douglas Missile Systems Company      |
These opinions are mine, mine, mine!  I  | curts@tmpcu.mdc.com  |
am not an instantiation of Std_Employee! | - Apple II Forever - |