6502/65C12/R65C02 Opcode Map ============================ http://mdfs.net/Docs/Comp/6502/OpCodeMap Author: J.G.Harston - Update: 0.10 - Date: 09-Sep-1997 0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F +--------+----------+---------+----------+-----------+---------+----------+---------+ 00 |BRK |ORA (zp,X)|hlt |slo (zp,X)|*TSB zp |ORA zp |ASL zp |slo zp | +--------+----------+---------+----------+-----------+---------+----------+---------+ 08 |PHP |ORA #n |ASL A |anc #n |*TSB abs |ORA abs |ASL abs |slo abs | +--------+----------+---------+----------+-----------+---------+----------+---------+ 10 |BPL rel |ORA (zp),Y|*ORA (zp)|slo (zp),Y|*TRB zp |ORA zp,X |ASL zp,X |slo zp,X | +--------+----------+---------+----------+-----------+---------+----------+---------+ 18 |CLC |ORA abs,Y |*INC A |slo abs,Y |*TRB abs |ORA abs,X|ASL abs,X |slo abs,X| +--------+----------+---------+----------+-----------+---------+----------+---------+ 20 |JSR abs |AND (zp,X)|hlt |rla (zp,X)|BIT zp |AND zp |ROL zp |rla zp | +--------+----------+---------+----------+-----------+---------+----------+---------+ 28 |PLP |AND #n |ROL A |anc #n |BIT abs |AND abs |ROL abs |rla abs | +--------+----------+---------+----------+-----------+---------+----------+---------+ 30 |BMI rel |AND (zp),Y|*AND (zp)|rla (zp),Y|*BIT zp,X |AND zp,X |ROL zp,X |rla zp,X | +--------+----------+---------+----------+-----------+---------+----------+---------+ 38 |SEC |AND abs,Y |*DEC A |rla abs,Y |*BIT abs,X |AND abs,X|ROL abs,X |rla abs,X| +--------+----------+---------+----------+-----------+---------+----------+---------+ 40 |RTI |EOR (zp,X)|hlt |sre (zp,X)|nop zp |EOR zp |LSR zp |sre zp | +--------+----------+---------+----------+-----------+---------+----------+---------+ 48 |PHA |EOR #n |LSR A |alr #n |JMP abs |EOR abs |LSR abs |sre abs | +--------+----------+---------+----------+-----------+---------+----------+---------+ 50 |BVC rel |EOR (zp),Y|*EOR (zp)|sre (zp),Y|nop zp,X |EOR zp,X |LSR zp,X |sre zp,X | +--------+----------+---------+----------+-----------+---------+----------+---------+ 58 |CLI |EOR abs,Y |*PHY |sre abs,Y |nop abs,X |EOR abs,X|LSR abs,X |sre abs,X| +--------+----------+---------+----------+-----------+---------+----------+---------+ 60 |RTS |ADC (zp,X)|hlt |rra (zp,X)|*STZ zp |ADC zp |ROR zp |rra zp | +--------+----------+---------+----------+-----------+---------+----------+---------+ 68 |PLA |ADC #n |ROR A |arr #n |JMP (abs) |ADC abs |ROR abs |rra abs | +--------+----------+---------+----------+-----------+---------+----------+---------+ 70 |BVS rel |ADC (zp),Y|*ADC (zp)|rra (zp),Y|*STZ zp,X |ADC zp,X |ROR zp,X |rra zp,X | +--------+----------+---------+----------+-----------+---------+----------+---------+ 78 |SEI |ADC abs,Y |*PLY |rra abs,Y |JMP (abs,X)|ADC abs,X|ROR abs,X |rra abs,X| +--------+----------+---------+----------+-----------+---------+----------+---------+ 80 |*BRA rel|STA (zp,X)|nop #n |sax (zp,X)|STY zp |STA zp |STX zp |sax zp | +--------+----------+---------+----------+-----------+---------+----------+---------+ 88 |DEY |*BIT #n |TXA |xaa #n |STY abs |STA abs |STX abs |sax abs | +--------+----------+---------+----------+-----------+---------+----------+---------+ 90 |BCC rel |STA (zp),Y|*STA (zp)|ahx (zp),Y|STY zp,X |STA zp,X |STX zpy |sax zpy | +--------+----------+---------+----------+-----------+---------+----------+---------+ 98 |TYA |STA abs,Y |TXS |tas abs,Y |*STZ abs |STA abs,X|*STZ abs,X|ahx abs,Y| +--------+----------+---------+----------+-----------+---------+----------+---------+ A0 |LDY #n |LDA (zp,X)|LDX #n |lax (zp,X)|LDY zp |LDA zp |LDX zp |lax zp | +--------+----------+---------+----------+-----------+---------+----------+---------+ A8 |TAY |LDA #n |TAX |lax #n |LDY abs |LDA abs |LDX abs |lax abs | +--------+----------+---------+----------+-----------+---------+----------+---------+ B0 |BCS rel |LDA (zp),Y|*LDA (zp)|lax (zp),Y|LDY zp,X |LDA zp,X |LDX zp,Y |lax zp,Y | +--------+----------+---------+----------+-----------+---------+----------+---------+ B8 |CLV |LDA abs,Y |TSX |las abs,Y |LDY abs,X |LDA abs,X|LDX abs,Y |lax abs,Y| +--------+----------+---------+----------+-----------+---------+----------+---------+ C0 |CPY #n |CMP (zp,X)|nop #n |dcp (zp,X)|CPY zp |CMP zp |DEC zp |dcp zp | +--------+----------+---------+----------+-----------+---------+----------+---------+ C8 |INY |CMP #n |DEX |axs #n |CPY abs |CMP abs |DEC abs |dcp abs | +--------+----------+---------+----------+-----------+---------+----------+---------+ D0 |BNE rel |CMP (zp),Y|*CMP (zp)|dcp (zp),Y|nop zp,X |CMP zp,X |DEC zp,X |dcp zp,X | +--------+----------+---------+----------+-----------+---------+----------+---------+ D8 |CLD |CMP abs,Y |*PHX |dcp abs,Y |nop abs,X |CMP abs,X|DEC abs,X |dcp abs,X| +--------+----------+---------+----------+-----------+---------+----------+---------+ E0 |CPX #n |SBC (zp,X)|nop #n |isc (zp,X)|CPX zp |SBC zp |INC zp |isc zp | +--------+----------+---------+----------+-----------+---------+----------+---------+ E8 |INX |SBC #n |NOP |sbb #n |CPX abs |SBC abs |INC abs |isc abs | +--------+----------+---------+----------+-----------+---------+----------+---------+ F0 |BEQ rel |SBC (zp),Y|*SBC (zp)|isc (zp),Y|nop zp,X |SBC zp,X |INC zp,X |isc zp,X | +--------+----------+---------+----------+-----------+---------+----------+---------+ F8 |SED |SBC abs,Y |*PLX |isc abs,Y |nop abs,X |SBC abs,X|INC abs,X |isc abs,X| +--------+----------+---------+----------+-----------+---------+----------+---------+ * indicates 65C12/R65C02 only, lower case indicates illegal opcodes. 65C12 executes illegal opcodes as NOPs. Illegal opcodes --------------- SLO Shift Left and OR ASL {adr}, ORA {adr} N Z C RLA Rotate Left and AND ROL {adr}, AND {adr} N Z C SRE Shift Right and EOR LSR {adr}, EOR {adr} N Z C RRA Rotate Right and ADC ROR {adr}, ADC {adr} N V Z C SAX Store A & X {adr} = combination of A & X LAX Load A & X LDA {adr>, LDX {adr} N Z DCP Decrement and Compare DEC {adr}, CMP {adr} N Z C ISC Increment and Subtract INC {adr}, SBC {adr} N V Z C ANC LDA and AND LDA (A AND {data}) N Z C ALR AND and LSR LDA (A AND {data}*2) N Z C ARR AND and ROR LDA (A AND {data}/2) N V Z C XAA TXA and AND LDA (X AND {data}) N Z highly unstable LAX LDA and TAX LDA {data}, TAX N Z highly unstable AXS SBC and TAX LDX (A&X-{data}-Cy) N Z C SUB SBC and NOP SBC {data} N V Z C AHX Store A&X&H ST(A&X&H) {adr} unstable in certain matters SHY Store Y&H ST(Y&H) {adr} unstable in certain matters SHX Store X&H ST(X&H) {adr} unstable in certain matters TAS Tranfer A&X&S, Store T(A&X)S, ST(A&X&H) {addr} unstable in certain matters LAS Load A,X,S LDA {addr}&S, TAX, TXS HLT Halts the CPU Notes ----- ANC: performs an AND operation only, but bit 7 is put into the carry, as if ASL/ROL has been executed. ARR: the V flag is set according to (A and #{imm})+#{imm}, bit 0 does NOT go into carry, but bit 7 is exchanged with the carry. AXS: performs CMP and DEX at the same time, so that the MINUS sets the flag like CMP, not SBC.