Full 6502 Opcode List Including Undocumented Opcodes ==================================================== File: Docs.Comp.65816.OpList - Update: 0.10 Author: J.G.Harston - Date: 25-11-1998 This is a complete list of what all the opcodes on the 6502, 65c12, R65c02 and 65816 actually do. The 6502 is used in the BBC series computers. The 65c12 is used in the Master series, and the Rockwell R65c02 is used in the 6502 co-processor. nn 6502 65C12 R65C02 65816 65Tube ------------------------------------------------------------------------------------- 00 BRK BRK BRK BRK 01 ORA (zp,X) ORA (zp,X) ORA (zp,X) ORA (dp,X) 02 * HALT - - COP num 03 * ASL-ORA (zp,X) - - ORA sr,S MOS_CLI 04 * NOP zp TSB zp TSB zp TSB dp 05 ORA zp ORA zp ORA zp ORA dp 06 ASL zp ASL zp ASL zp ASL dp 07 * ASL-ORA zp - - ORA [dp] MOS_SWI 08 PHP PHP PHP PHP 09 ORA #n ORA #n ORA #n ORA #n 0A ASL A ASL A ASL A ASL A 0B * AND #n-b7->Cy - - PHD 0C * NOP abs TSB abs TSB abs TSB abs 0D ORA abs ORA abs ORA abs ORA abs 0E ASL abs ASL abs ASL abs ASL abs 0F * ASL-ORA abs - BBR 0,zp,rel ORA long 10 BPL rel BPL rel BPL rel BPL rel 11 ORA (zp),Y ORA (zp),Y ORA (zp),Y ORA (dp),Y 12 * HALT ORA (zp) ORA (zp) ORA (dp) 13 * ASL-ORA (zp),Y - - ORA (sr,S),Y MOS_BYTE 14 * NOP zp TRB zp TRB zp TRB dp 15 ORA zp,X ORA zp,X ORA zp,X ORA dp,X 16 ASL zp,X ASL zp,X ASL zp,X ASL dp,X 17 * ASL-ORA abs,X - - ORA [dp],Y 18 CLC CLC CLC CLC 19 ORA abs,Y ORA abs,Y ORA abs,Y ORA abs,Y 1A * NOP INC A INC A INC A 1B * ASL-ORA abs,Y - - TCS 1C * NOP abs TRB abs TRB abs TRB abs 1D ORA abs,X ORA abs,X ORA abs,X ORA abs,X 1E ASL abs,X ASL abs,X ASL abs,X ASL abs,X 1F * ASL-ORA abs,X - BBR 1,zp,rel ORA long,X 20 JSR abs JSR abs JSR abs JSR abs 21 AND (zp,X) AND (zp,X) AND (zp,X) AND (dp,X) 22 * HALT - - JSR long 23 * ROL-AND (zp,X) - - AND sr,S MOS_WORD 24 BIT zp BIT zp BIT zp BIT dp 25 AND zp AND zp AND zp AND dp 26 ROL zp ROL zp ROL zp ROL dp 27 * ROL-AND zp - - AND [dp] 28 PLP PLP PLP PLP 29 AND #n AND #n AND #n AND #n 2A ROL A ROL A ROL A ROL A 2B * AND #n-b7->Cy - - PLD 2C BIT abs BIT abs BIT abs BIT abs 2D AND abs AND abs AND abs AND abs 2E ROL abs ROL abs ROL abs ROL abs 2F * ROL-AND abs - BBR 0,zp,rel AND long 30 BMI rel BMI rel BMI rel BMI rel 31 AND (zp),Y AND (zp),Y AND (zp),Y AND (dp),Y 32 * HALT AND (zp) AND (zp) AND (dp) 33 * ROL-AND (zp),Y - - AND (sr,S),Y MOS_WRCH 34 * NOP zp BIT zp,X BIT zp,X BIT dp,X 35 AND zp,X AND zp,X AND zp,X AND dp,X 36 ROL zp,X ROL zp,X ROL zp,X ROL dp,X 37 * ROL-AND zp,X - - AND [dp],Y 38 SEC SEC SEC SEC 39 AND abs,Y AND abs,Y AND abs,Y AND abs,Y 3A * NOP DEC A DEC A DEC A 3B * ROL-AND abs,Y - - TSC 3C * NOP abs BIT abs,X BIT abs,X BIT abs,X 3D ORA abs,X ORA abs,X ORA abs,X AND abs,X 3E ASL abs,X ASL abs,X ASL abs,X ROL abs,X 3F * ROL-AND abs,X - BBR 1,zp,rel AND long,X 40 RTI RTI RTI RTI 41 EOR (zp,X) EOR (zp,X) EOR (zp,X) EOR (dp,X) 42 * HALT - - WDM num 43 * LSR-EOR (zp,X) - - EOR sr,S MOS_RDCH 44 * NOP zp - - MVP src,dest 45 EOR zp EOR zp EOR zp EOR dp 46 LSR zp LSR zp LSR zp LSR dp 47 * LSR-EOR zp - - EOR [dp] 48 PHA PHA PHA PHA 49 EOR #n EOR #n EOR #n EOR #n 4A LSR A LSR A LSR A LSR A 4B * AND #n-LSR A - - PHK 4C JMP abs JMP abs JMP abs JMP abs 4D EOR abs EOR abs EOR abs EOR abs 4E LSR abs LSR abs LSR abs LSR abs 4F * LSR-EOR abs - BBR 0,zp,rel EOR long 50 BVC rel BVC rel BVC rel BVC rel 51 EOR (zp),Y EOR (zp),Y EOR (zp),Y EOR (dp),Y 52 * HALT EOR (zp) EOR (zp) EOR (dp) 53 * LSR-EOR (zp),Y - - EOR (sr,S),Y MOS_FILE 54 * NOP zp - - MVN src,dest 55 EOR zp,X EOR zp,X EOR zp,X EOR dp,X 56 LSR zp,X LSR zp,X LSR zp,X LSR dp,X 57 * LSR-EOR abs,X - - EOR [dp],Y 58 CLI CLI CLI CLI 59 EOR abs,Y EOR abs,Y EOR abs,Y EOR abs,Y 5A * NOP PHY PHY PHY 5B * LSR-EOR abs,Y - - TCD 5C * NOP abs - - JMP long 5D EOR abs,X EOR abs,X EOR abs,X EOR abs,X 5E LSR abs,X LSR abs,X LSR abs,X LSR abs,X 5F * LSR-EOR abs,X - BBR 1,zp,rel EOR long,X 60 RTS RTS RTS RTS 61 ADC (zp,X) ADC (zp,X) ADC (zp,X) ADC (dp,X) 62 * HALT - - PER label 63 * ROR-ADC (zp,X) - - ADC sr,S MOS_ARGS 64 * NOP zp STZ zp STZ zp STZ dp 65 ADC zp ADC zp ADC zp ADC dp 66 ROR zp ROR zp ROR zp ROR dp 67 * ROR-ADC zp - - ADC [dp] 68 PLA PLA PLA PLA 69 ADC #n ADC #n ADC #n ADC #n 6A ROR A ROR A ROR A ROR A 6B * AND #n-ROR A - - RTL 6C JMP (abs) JMP (abs) JMP (abs) JMP (abs) 6D ADC abs ABC abs ADC abs ADC abs 6E ROR abs ROR abs ROR abs ROR abs 6F * ROR-ADC abs - BBR 0,zp,rel ADC long 70 BVS rel BVS rel BVS rel BVS rel 71 ADC (zp),Y ADC (zp),Y ADC (zp),Y ADC (dp),Y 72 * HALT ADC (zp) ADC (zp) ADC (dp) 73 * ROR-ADC (zp),Y - - ADC (sr,S),Y MOS_BGET 74 * NOP zp STZ zp,X STZ zp,X STZ dp,X 75 ADC zp,X ADC zp,X ADC zp,X ADC dp,X 76 ROR zp,X ROR zp,X ROR zp,X ROR dp,X 77 * ROR-ADC abs,X - - ADC [dp],Y 78 SEI SEI SEI SEI 79 ADC abs,Y ADC abs,Y ADC abs,Y ADC abs,Y 7A * NOP PLY PLY PLY 7B * ROR-ADC abs,Y - - TDC 7C * NOP abs JMP (abs,X) JMP (abs,X) JMP (abs,X) 7D ADC abs,X ADC abs,X ADC abs,X ADC abs,X 7E ROR abs,X ROR abs,X ROR abs,X ROR abs,X 7F * ROR-ADC abs,X - BBR 1,zp,rel ADC long,X 80 * NOP zp BRA rel BRA rel BRA rel 81 STA (zp,X) STA (zp,X) STA (zp,X) STA (dp,X) 82 * HALT - - BRL label 83 * STA-STX (zp,X) - - STA sr,S MOS_BPUT 84 STY zp STY zp STY zp STY dp 85 STA zp STA zp STA zp STA dp 86 STX zp STX zp STX zp STX dp 87 * STA-STX zp - - STA [dp] 88 DEY DEY DEY DEY 89 * NOP zp BIT #n BIT #n BIT #n 8A TXA A TXA TXA TXA 8B * TXA-AND #n - - PHB 8C STY abs STY abs STY abs STY abs 8D STA abs STA abs STA abs STA abs 8E STX abs STX abs STX abs STX abs 8F * STA-STX abs - BBR 0,zp,rel STA long 90 BCC rel BCC rel BCC rel BCC rel 91 STA (zp),Y STA (zp),Y STA (zp),Y STA (dp),Y 92 * HALT STA (zp) STA (zp) STA (dp) 93 * STA-STX (zp),Y - - STA (sr,S),Y MOS_GBPB 94 STY zp STY zp STY zp STY dp,X 95 STA zp,X STA zp,X STA zp,X STA dp,X 96 STX zp,Y STX zp,Y STX zp,Y STX dp,Y 97 * STA-STX zp,Y - - STA [dp],Y 98 TYA TYA TYA TYA 99 STA abs,Y STA abs,Y STA abs,Y STA abs,Y 9A TXS TXS TXS TXS 9B * STA-STX abs,Y - - TXY 9C * STA-STX abs,X STZ abs - STZ abs 9D STA abs,X STA abs,X STA abs,X STA abs,X 9E * STA-STX abs,X STZ abs,X STZ abs,X STZ abs,X 9F * STA-STX abs,X - BBR 1,zp,rel STA long,X A0 LDY #n LDY #n LDY #n LDY #n A1 LDA (zp,X) LDA (zp,X) LDA (zp,X) LDA (dp,X) A2 LDX #n LDX #n LDX #n LDX #n A3 * LDA-LDX (zp,X) - - LDA sr,S MOS_FIND A4 LDY zp LDY zp LDY zp LDY dp A5 LDA zp LDA zp LDA zp LDA dp A6 LDX zp LDX zp LDX zp LDX dp A7 * LDA-LDX zp - - LDA [dp] A8 TAY TAY TAY TAY A9 LDA #n LDA #n LDA #n LDA #n AA TAX TAX TAX TAX AB * LDA-LDX - - PLB AC LDY abs LDY abs LDY abs LDY abs AD LDA abs LDA abs LDA abs LDA abs AE LDX abs LDX abs LDX abs LDX abs AF * LDA-LDX abs - BBR 0,zp,rel LDA long B0 BCS rel BCS rel BCS rel BCS rel B1 LDA (zp),Y LDA (zp),Y LDA (zp),Y LDA (dp),Y B2 * HALT LDA (zp) LDA (zp) LDA (dp) B3 * LDA-LDX (zp),Y - - LDA (sr,S),Y MOS_QUIT B4 LDY zp LDY zp LDY zp LDY dp,X B5 LDA zp,X LDA zp,X LDA zp,X LDA dp,X B6 LDX zp,Y LDX zp,Y LDX zp,Y LDX dp,Y B7 * LDA-LDX zp,Y - - LDA [dp],Y B8 CLV CLV CLV CLV B9 LDA abs,Y LDA abs,Y LDA abs,Y LDA abs,Y BA TSX TSX TSX TSX BB * LDA-LDX abs,Y - - TYX BC LDY abs,X LDY abs,X LDY abs,X LDY abs,X BD LDA abs,X LDA abs,X LDA abs,X LDA abs,X BE LDX abs,Y LDX abs,Y LDX abs,Y LDX abs,Y BF * LDA-LDX abs,Y - BBR 1,zp,rel LDA long,X C0 CPY #n CPY #n CPY #n CPY #n C1 CMP (zp,X) CMP (zp,X) CMP (zp,X) CMP (dp,X) C2 * HALT - - REP #n C3 * DEC-CMP (zp,X) - - CMP sr,S MOS_LANG C4 CPY zp CPY zp CPY zp CPY dp C5 CMP zp CMP zp CMP zp CMP dp C6 DEC zp DEC zp DEC zp DEC dp C7 * DEC-CMP zp - - CMP [dp] C8 INY INY INY INY C9 CMP #n CMP #n CMP #n CMP #n CA DEX DEX DEX DEX CB * SBX #n - - WAI CC CPY abs CPY abs CPY abs CPY abs CD CMP abs CMP abs CMP abs CMP abs CE DEC abs DEC abs DEC abs DEC abs CF * DEC-CMP abs - BBR 0,zp,rel CMP long D0 BNE rel BNE rel BNE rel BNE rel D1 CMP (zp),Y CMP (zp),Y CMP (zp),Y CMP (dp),Y D2 * HALT CMP (zp) CMP (zp) CMP (dp) D3 * DEC-CMP (zp),Y - - CMP (sr,S),Y D4 * NOP zp - - PEI (dp) D5 CMP zp,X CMP zp,X CMP zp,X CMP dp,X D6 DEC zp,X DEC zp,X DEC zp,X DEC dp,X D7 * DEC-CMP zp,X - - CMP [dp],Y D8 CLD CLD CLD CLD D9 CMP abs,Y CMP abs,Y CMP abs,Y CMP abs,Y DA * NOP PHX PHX PHX DB * DEC-CMP abs,Y - - STP DC * NOP abs - - JMP [abs] DD CMP abs,X CMP abs,X CMP abs,X CMP abs,X DE DEC abs,X DEC abs,X DEC abs,X DEC abs,X DF * DEC-CMP abs,X - BBR 1,zp,rel CMP long,X E0 CPX #n CPX #n CPX #n CPX #n E1 SBC (zp,X) SBC (zp,X) SBC (zp,X) SBC (dp,X) E2 * HALT - - SEP E3 * INC-SBC (zp,X) - - SBC sr,S E4 CPX zp CPX zp CPX zp CPX dp E5 SBC zp SBC zp SBC zp SBC dp E6 INC zp INC zp INC zp INC dp E7 * INC-SBC zp - - SBC [dp] E8 INX INX INX INX E9 SBC #n SBC #n SBC #n SBC #n EA NOP NOP NOP NOP EB SBC #n SBC #n SBC #n XBA EC CPX abs CPX abs CPX abs CPX abs ED SBC abs SBC abs SBC abs SBC abs EE INC abs INC abs INC abs INC abs EF * INC-SBC abs - BBR 0,zp,rel SBC long F0 BEQ rel BEQ rel BEQ rel BEQ rel F1 SBC (zp),Y SBC (zp),Y SBC (zp),Y SBC (dp),Y F2 * HALT SBC (zp) SBC (zp) SBC (dp) F3 * INC-SBC (zp),Y - - SBC (sr,S),Y F4 * NOP zp - - PEA abs F5 SBC zp,X SBC zp,X SBC zp,X SBC dp,X F6 INC zp,X INC zp,X INC zp,X INC dp,X F7 * INC-SBC zp,X - - SBC [dp],Y F8 SED SED SED SED F9 SBC abs,Y SBC abs,Y SBC abs,Y SBC abs,Y FA * NOP PLX PLX PLX FB * INC-SBC abs,Y - - XCE FC * NOP abs - - JSR (abs,X)) FD SBC abs,X SBC abs,X SBC abs,X SBC abs,X FE INC abs,X INC abs,X INC abs,X INC abs,X FF * INC-SBC abs,X - BBR 1,zp,rel SBC long,X Notes on extra opcodes ---------------------- Opcodes with a * by them in the above list are 'illegal'. Ones listed as ? are probably the same as the 6502 code, but so far I have not yet tested them. The effects of the opcodes are probably due to the way the instruction logic is decoded within the 65x02. Most instructions do not have full sets of bits turned on, and are of the form xx01 or xx10. This suggests that the bits are used to select the internal function, and so if a bit pattern of xx11 appears, both functions are selected, and both functions get performed. Some instructions do not follow this exactly, as data contention occurs. I have yet to fully find out what, for instance, STA-STX does, as it cannot store both bytes into one byte of memory. As more information comes to light about the exact actions of some opcodes, and as I compile fuller data on the 65c12 and r65c02 I will update this document. Effects of the extra opcodes ---------------------------- HALT - Halts the processor, only a RESET will restart. NOP - Does nothing, may apparently take an address, and so can effectively skips more than just one byte. The addressing modes shown are extrapolated from the other instructions the NOPs appear within. ASL-ORA - Performs an ASL on the data, and then ORAs the result into the A register. AND #n-b7->Cy - ANDs A with the data, and copies bit 7 of A to the Carry flag ROL-AND - Performs a ROL on the data, and then ANDs the result into the A register. LSR-EOR - Performs a LSR on the data, and then EORs the result into the A register ROR-ADC - Performs a ROR on the data, and then ADCs the result into the A register STA-STX - Stores the A register and the X register into memory. I need to test this myself, to find out exactly which or what is stored, as obviously, both cannot be stored TXA-AND #n - Tranfers the X register into the A register, and then ANDs it with #n LDA-LDX - Loads the data into both the A register and the X register DEC-CMP - Decrements the data, and then compares the A register with the result INC-SBC - Increments the data, and then subtracts the result from the A register 6502 Emulators -------------- Most 6502 emulators seem to have chosen &x3 as the opcodes to communicate with the host system, ie the extra (zp,X) addressing mode instructions. Document History ---------------- 25-Nov-1998 v0.10 Initial full version, after months tracking down various sources. 12-Feb-2006 v0.11 Found original Acorn User article. References ---------- Undocumented 6502 opcodes: "Extra Instructions Of The 65XX Series CPU" Adam Vardy (abe0084@infonet.st-johns.nf.ca) "6502 And All That", Eight Bits feature, Acorn User, June 1991. 65c12 and R65c02 opcodes: "The New Advanced User Guide", Dickens & Holmes, Adder, 1987. Undocumented 65c12 and R65c02 opcodes: Investigative research by JGH, 1998.