Register state on code entry
                        ============================
                        
When machine code is loaded from a file or ROM and entered by the MOS or a
filing system, the registers are set to a certain state on entry to the code.
Different systems are patchy in the actual implementation.

Code should be entered as follows:

  Primary register=0 - entering raw code
  Primary register=1 - entering code with a header
  Carry flag clear   - entering from RESET
  Carry flag set     - entering from OSCLI

The primary register is the main accumulator, for example, the A, AL, R0
register.

6502 Host MOS
-------------
Language entry at &8000 or &0400:
 A=0 - no language ROM found
 A=1 - code with a header, ie a language ROM
 CC  - reset
 CS  - oscli/osbyte 142

Filing system entry:
 Filing systems are inconsistant about how they enter code in the 6502 host
 system. More or less all filing systems do not check for a code header, and
 those that set up the registers enter all code with A=1 and other registers
 and the flags in an indeterminate state.

6502/65C102 Second Processor
----------------------------
 A=1 - raw code or code with a header
 Cy  - indeterminate
 
6502/65C102 Second Processor v1.11
----------------------------------
 A=0 - raw code
 A=1 - code with a header
 CC  - reset
 CS  - oscli/osbyte 142

65816/6502 ReCoPro (John Kortink)
---------------------------------
 A=0 - raw code
 A=1 - code with a header
 CC  - reset
 CS  - oscli/osbyte 142

Z80 Second Processor
--------------------
 A=%00000001, NZ, CC - code with a header, oscli, v1.20 client
 A=%????????, NZ, Cy=indeterminate - raw code, stack unbalanced, v1.20 client
 A=%x1xx1xxx, NZ, CC - code with a header, reset, v1.20 client

 A=%00000001, NZ, CC - code header, oscli, v1.2x+bbcbasic
 A=%????????, Z, CC, raw code, stack balanced, v1.2x+bbcbasic
 A=%x1xx1xxx, NZ, CC - code header, reset, v1.2x+bbcbasic

 A=%00000001, Z, CC, code header, oscli, v1.21
 A=%????????, Z, CC, raw code, stack balanced, v1.21
 A=%01001000, Z, CC, code header, reset, v1.21

 A=%00000001, Z, CC, code header, oscli, v2.00 client
 A=%????????, NZ, Cy=indeterminate - raw code, stack balanced, v2.00 client
 A=%000010x0, Z, CC, code header, reset, v2.00 client

Code with a header:
 A=1  - oscli
       NZ - v1.20
       Z  - v1.21, v2.00
 A<>1 - reset
       NZ - v1.20
       Z  - v1.21, v2.00

Raw code:
 A=anything
       NZ - unbalanced stack on v1.20 or balanced stack on v2.00
       Z  - balanced stack

6809 Second Processor
---------------------
 A=0 - raw code
 A=1 - code header
 X=>command line tail
 CS=entering from OSCLI
 CC=entering from RESET

80x86 Second Processor
----------------------
AL<>0, NZ, raw code, oscli
AL=0, Z, raw code, soft reset
AL=1, Z, CC, code header, oscli
AL=11, Z, CC, code header, reset

32000 Second Processor
----------------------
code header:
     R1=0 initial entry (power-on or <ctrl-break>)
     R1=1 entry after any other variety of <break>
     R1=2 entry via OS_EXIT
     R1=3 entry via OS_CLI
raw code:

ARM Second Processor
--------------------
R0=0 - raw code
R0=1 - code header

PDP11 Second Processor
----------------------
R0=0 raw code
R0=1 code with a ROM header
R1=>command line tail
Cy=0 entered from RESET
Cy=1 entered from OSCLI/OSBYTE