2681 DUART
                                  ==========
     The 2681 DUART is used in the Jafa Electron Serial Interface

+=========+============================+==============================+
|         |           Write            |             Read             |
+=========+============================+==============================+
| base+0  |                   Mode Register A1/B1                     |
| PORT A  | b7:   RxRTS control   0=No, 1=Yes                         |
|         | b6:   RxINT select    0=RdRDY, 1=RxFull                   |
| base+8  | b5:   Error mode      0=char, 1=block                     |
| PORT B  | b4-3: Parity          00=Yes, 01=Forced, 10=None, 11=Multi|
|         | b5:   Parity          0=Even, 1=Odd                       |
|         | b1-0: Character size  00=5, 01=6, 10=7, 11=8              |
|         |                                                           |
|         |                   Mode Register A2/B2                     |
|         | b7-6: Channel         00=Normal, 10=Local Loop            |
|         |                       01=Echo,   11=Remote Loop           |
|         | b5:   TxRTS control   0=No, 1=Yes                         |
|         | b4:   TxCTS enable    0=No, 1=Yes                         |
|         | b3-0: Stop bit        0=0.563 ... F=2.000                 |  
+---------+----------------------------+------------------------------+
| base+1  | Clock Select Register A/B  | Status Register A/B          |
| PORT A  |  b7-4: Rx baud             |  b7: Break received          |
|         |  b3-0: Tx baud             |  b6: Receive Framing error   |
| base+9  |   If ACR.b7=0:             |  b5: Receive Parity Error    |
| PORT B  |    50,110,134,200,300,600, |  b4: Receive data overrun    |
|         |    1200,1050,2400,4800,    |  b3: Transmit Register Empty |
|         |    7200,9600,38000,timer,  |  b2: Transmit Register Ready |
|         |   If ACR.b7=1:             |  b1: Receive Register Full   |
|         |    75,110,134,150,300,600, |  b0: Receive Register Ready  |
|         |    1200,2000,2400,4800,    |                              |
|         |    1800,9600,19200,timer,  |                              |
|         | TxA 14: IP3x16  15: IP3x1  |                              |
|         | RxA 14: IP4x16  15: IP4x1  |                              |
|         | TxB 14: IP5x16  15: IP5x1  |                              |
|         | RxB 14: IP6x16  15: IP6x1  |                              |
+---------+----------------------------+------------------------------+
| base+2  | Command Register A/B       | Reserved (BRG Extend)        |
| PORT A  | b6-b4: Command             |                              |
|         |  000=null     001=ModeReg 1|                              |
| base+10 |  010=RxReset  011=TxReset  | Reserved (1x16x Test)        |
| PORT B  |  100=Reset Error           |                              |
|         |  101=Reset Break           |                              |
|         |  110=Start Brk 111=End Brk |                              |
|         | b3: Tx Disable             |                              |
|         | b2: Tx Enable              |                              |
|         | b1: Rx Disable             |                              |
|         | b0: Rx Enable              |                              |
+---------+----------------------------+------------------------------+
| base+3  | Transmit Data Register A   | Receive Data Register A      |
| PORT A  |                            |                              |
|         |                            |                              |
| base+11 | Transmit Data Register B   | Receive Data Register B      | 
| PORT B  |                            |                              |
+=========+============================+==============================+
| base+4  | Aux. Control Register      | Input Port Change Register   |
|         | b7:   Baud Select          |  b7: IP3 changed  b3: IP3    |
|         | b6-4: Counter/Timer        |  b6: IP2 changed  b2: IP2    |
|         | b3:   IP3 change enable    |  b5: IP1 changed  b1: IP1    |
|         | b2:   IP2 change enable    |  b4: IP0 changed  b0: IP0    |
|         | b1:   IP1 change enable    |                              |
|         | b0:   IP0 change enable    |                              |
+---------+----------------------------+------------------------------+
| base+5  | Interupt Enable Register   | Interupt Status Register     |
|         |  b7: IntEnable/Input Port     b3: Counter Ready           |
|         |  b6: BreakB changed           b2: BreakA changed          |
|         |  b5: RxRDYB/RxFullB           b1: RxRDYA/RxFullA          |
|         |  b4: TxRDYB                   b0: TxRDYA                  |
+---------+----------------------------+------------------------------+
| base+6  |               Counter/Time Upper Register                 |
+---------+----------------------------+------------------------------+
| base+7  |               Counter/Time Lower Register                 |
+=========+============================+==============================+
| base+12 | reserved (scratch)         | reserved (scratch)           |
+---------+----------------------------+------------------------------+
| base+13 | Output Port Config. Reg.   | Input Port Register          |
|         |   0=bit set from OPR       |  b7:   always 1              |
|         |   1=bit set from status    |  b6-0: Input port            |
|         | b7: TxRDYB                 |                              |
|         | b6: TxRDYA                 |                              |
|         | b5: RxRDYB/RxFullB         |                              |
|         | b4: RxRDYA/RxFullA         |                              |
|         | b3: TxCB/RxCB              |                              |
|         | b2: C/T Output             |                              |
|         | b1: TxCA/RxCA              |                              |
|         | b0: TxCA(16x)              |                              |
+---------+----------------------------+------------------------------+
| base+14 | Set Output Port Bits       | Start Counter                |
+---------+----------------------------+------------------------------+
| base+15 | Reset Output Port Bits     | Stop Counter                 |
+=========+============================+==============================+

Base  Device
----------------------------------------------
FC60  Jafa Electron Serial Interface
      OP0  -> RTS output
      OP1  -> nc
      IP2  <- CTS input
      RXDB <- nc
      TXDB -> nc