6532 RAM/IO/Timer
                                  =================

+----------+-------------------------------+-------------------------------+
|          |            Write              |             Read              |
+==========+===============================+===============================+
| base+&00 |                       128 bytes of SRAM                       |
+----------+-------------------------------+-------------------------------+
| base+&80 |                        Data Register A                        |
| base+&81 |                   Data direction register A                   |
| base+&82 |                        Data Register B                        |
| base+&83 |                   Data direction register B                   |
+----------+-------------------------------+-------------------------------+
| base+&84 | Write -ve edge detect IRQ Off | Read timer, IRQ Off           |
| base+&85 | Write +ve edge detect IRQ Off | Read IRQ flags register       |
| base+&86 | Write -ve edge detect IRQ On  |                               |
| base+&87 | Write +ve edge detect IRQ On  |                               |
| base+&88 |                               |                               |
| base+&89 |                               |                               |
| base+&8A |                               |                               |
| base+&8B |                               |                               |
| base+&8C |                               | Read timer, IRQ On            |
| base+&8D |                               |                               |
| base+&8E |                               |                               |
| base+&8F |                               |                               |
+----------+-------------------------------+-------------------------------+
| base+&90 |                               |                               |
| base+&91 |                               |                               |
| base+&92 |                               |                               |
| base+&93 |                               |                               |
| base+&94 | Write timer div 1, IRQ Off    |                               |
| base+&95 | Write timer div 8, IRQ Off    |                               |
| base+&96 | Write timer div 64, IRQ Off   |                               |
| base+&97 | Write timer div 1024, IRQ Off |                               |
| base+&98 |                               |                               |
| base+&99 |                               |                               |
| base+&9A |                               |                               |
| base+&9B |                               |                               |
| base+&9C | Write timer div 1, IRQ On     |                               |
| base+&9D | Write timer div 8, IRQ On     |                               |
| base+&9E | Write timer div 64, IRQ On    |                               |
| base+&9F | Write timer div 1024, IRQ On  |                               |
+==========+===============================+===============================+


          You can get a more logical address range by connecting
                        CPU4->A3 CPU3->A2 CPU2->A4
+----------+-------------------------------+-------------------------------+
|          |            Write              |             Read              |
+==========+===============================+===============================+
| base+&00 |                             SRAM                              |
+----------+-------------------------------+-------------------------------+
| base+&80 |                        Data Register A                        |
| base+&81 |                   Data direction register A                   |
| base+&82 |                        Data Register B                        |
| base+&83 |                   Data direction register B                   |
+----------+-------------------------------+-------------------------------+
| base+&90 | Write -ve edge detect IRQ Off | Read timer, IRQ Off           |
| base+&91 | Write +ve edge detect IRQ Off | Read IRQ flags register       |
| base+&92 | Write -ve edge detect IRQ On  |                               |
| base+&93 | Write +ve edge detect IRQ On  |                               |
+----------+-------------------------------+-------------------------------+
| base+&94 |                               | Read timer, IRQ On            |
| base+&95 |                               |                               |
| base+&96 |                               |                               |
| base+&97 |                               |                               |
+----------+-------------------------------+-------------------------------+
| base+&98 | Write timer div 1, IRQ Off    |                               |
| base+&99 | Write timer div 8, IRQ Off    |                               |
| base+&9A | Write timer div 64, IRQ Off   |                               |
| base+&9B | Write timer div 1024, IRQ Off |                               |
+----------+-------------------------------+-------------------------------+
| base+&9C | Write timer div 1, IRQ On     |                               |
| base+&9D | Write timer div 8, IRQ On     |                               |
| base+&9E | Write timer div 64, IRQ On    |                               |
| base+&9F | Write timer div 1024, IRQ On  |                               |
+==========+===============================+===============================+



Base  Device
----------------------------------------------
1A10  Elecktor Junior Computer
FA10  Elecktor Junior Computer with modified memory map