6845 CRTC ========= +--------+---------------------------------------+----------------------------------+ | | Write | Read | +========+=======================================+==================================+ | base+0 | Register Select | Status where supported | | | b7-b5: ignored | b7: | | b4-b0: register | b6: set if LPSTB set | | | | b5: set during vertical blanking | | | | when character line >= R6 | | | | all other bits read as 0, but | | | | see notes | +--------+---------------------------------------+----------------------------------+ | base+1 | Write to register | Read from register | +========+=======================================+==================================+ +--------+---------------------------------------+----------------------------------+ |Register| Write | Read | +========+=======================================+==================================+ | 0 | b7-b0: Horizontal total characters -1 | | +--------+---------------------------------------+ | | 1 | b7-b0: Horizontal displayed characters| | +--------+---------------------------------------+ | | 2 | b7-b0: Horizontal sync position -1 | | +--------+---------------------------------------+ | | 3 | b7-b4: Vertical sync width, 0=illegal | | | | b3-b0: Horizontal sync width, 0=16 | | +--------+---------------------------------------+ | | 4 | b7: ignored | | | | b6-b0: Vertical total characters -1 | | +--------+---------------------------------------+ | | 5 | b7-b5: ignored | | | | b4-b0: Vertical total adjust in lines | | +--------+---------------------------------------+ | | 6 | b7: ignored | experimentation shows reading | | | b6-b0: Vertical displayed characters | registers returns &00 | +--------+---------------------------------------+ | | 7 | b7: ignored | | | | b6-b0: Vertical sync position -1 | | +--------+---------------------------------------+ | | 8 | b7-b6: Cursor delay, %11=disable cursor R6545: b6=ignored | | | b6-b4: Character delay, %11=disable display R6545: b5=cursor delay | | | R6545: b4=character display | | | b3-b2: ignored R6545: b2=binary/row+column | | | b1: Video mode off/on R6545: b1=ignored | | | b0: Interlace mode off/on R6545: b0=must be 0 | +--------+---------------------------------------+ | | 9 | b7-b5: ignored | | | | b4-b0: Scan lines per character -1 | | +--------+---------------------------------------+ | | 10 | b7: ignored | | | | b6: blink off/on | | | | b5: if b6=0: if b6=1: | | | | cursor on/off blink slow/fast | | | | This gives: %00 steady cursor | | | | %01 cursor off | | | | %10 blink slow | | | | %11 blink fast | | | | b4-b0: Cursor start line | | +--------+---------------------------------------+ | | 11 | b7-b5: ignored | | | | b4-b0: Cursor end line | | +--------+---------------------------------------+----------------------------------+ | 12 | b5-b0: Screen start address high, b7-b6 read as 0 | | 13 | b7-b0: Screen start address low | | 14 | b5-b0: Cursor address high, b7-b6 read as 0 | | 15 | b7-b0: Cursor address low | +--------+---------------------------------------+----------------------------------+ | 16 | ?? | b7-b6: read as 0 | | | | b5-b0: Light pen address high | | 17 | ?? | b7-b0: Light pen address low | +--------+---------------------------------------+----------------------------------+ | 18 | Cursor width in pixels | | | | (BBFW via VDU 23;18) | | | | | | +--------+---------------------------------------+ experimentation shows reading | | 19-30 | ?? | registers returns &00 | +--------+---------------------------------------+----------------------------------+ | 31 | | Returns &FF on UM6845R, returns | | | | &00 on others | +========+=======================================+==================================+ Notes: The BBC series require the 6845S variant as the VDU drivers rely on: * R3 Vertical Sync Width programmable * R6 Vertical Displayed any odd/even value, to set total=25 in MODE 3,6,7. * R8 display delay timing programmable The BBC API to write to the 6845 CRTC is VDU 23,0,register,value,0,0,0,0,0,0. This also modifies writes to R7,R8,R10 to take account of the *TV and VDU 23,1 settings. The cursor state in R10 is changed with VDU 23,1,state,0,0,0,0,0,0,0. Hitachi and UMC 6845s allow reading a Status register. Documentation states that bit 7 and bits 4-0 are read as zero, but experimentation shows bit 7 read as zero and bits 4-0 usually zero, but randomly one. Differences between 6845 varients 6845R vertical displayed = total/2 6845S vertical displayed = total, required to be able to set total=25 6845R scan lines per character forced to be even 6845S scan lines per character odd or even 6845R cursor only displayed in odd/even fields matching start line 6845S cursor displayed in all fields 6845R VSync in R3 fixed at 16 6845S VSync in R3 programmable 6845R R8 only supports Video and Sync 6845S R8 also supports display delay timing 6845R R12/R13 display start write only 6834S R12/R13 display start read/write UM6845 UM6845R MC6845 R6545 R3: VSync/HSync HSync only HSync only R31: reads as FF R12/13 Status status reg status Part number Manufacturer Type HD6845S Hitachi 0 can't read from base+0 R12/13 read/write UM6845 UMC 0 can't read from base+0 R12/13 read/write UM6845R UMC 1 can read status from base+0 R12/13 write only MC6845 Motorola 2 can't read from base+0 R12/13 write only AMS40489 Amstrad 3 read from base+0 reads register R12/13 read/write 40226 Amstrad 4 read from base+0 reads register R12/13 read/write HSYNC=1 | HSYNC=0 | | DEN=0 DEN=1 DEN=0 | | | VSYNC=1 +-------------------------+---------------- | BORDER | DEN=0 | +-----------+ | | | | | | | DISPLAY | | DEN=1 VSYNC=0 | | | | | +-----------+ | | BORDER | DEN=0 +-------------------------+---------------- 6502org_logo André's 8-bit Pages Projects Code Resources Tools Forum (by Google) Home > Hardware Info > CRTC 6545/6845 CRTC operation Differences between models CRTC system integration CRTC internals Composite video generation CBM PET test programs >CS/A VDC board >Creative use Differences of CRTC models (C) 1999-2006 André Fachat I have gathered together the differences between CRTC models from various sources. The docs to Rockwell 6545-1 Motorola 6845, 6845-1, 68A45, 68A45-1, 68B45, 68B45-1 Hitachi 46505 Commodore 6545-1 have been taken from http://www.zimmers.net/anonftp/pub/cbm/documents/chipdata/index.html. The Motorola chips are actually only two different chips, namely 6845 and 6845-1, with different speed ratings ("", "A", "B"). I will therefore only use the names without speed ratings. I checked the Motorola 6845 with my private docs, and added the Rockwell 6545, 6545E docs from my Rockwell International 1987 Controller Products Data Book. Again the only difference I found between those two chips was the maximum allowed clock frequency (2.5 MHz vs. 3.7 MHz for the R6545E). I will not go into details that are common to all chips. If you have further questions please refer to the CRTC documentation on http://www.zimmers.net/anonftp/pub/cbm/documents/chipdata/index.html and http://www.6502.org/documents/datasheets/. Table of content Pinout Status Register Register File The major differences in the register file R3, sync widths R8, Mode Control Pinout Although the pin naming is different, the pinout itself is the same for all chips, and all pins have the same meaning. Status Register The Status register is read when the register select (RS) pin is low (when writing to this address, the index in the CRTC register file is written). Commodore 6545-1, Rockwell 6545-1 Bits 0-4: not used Bit 5: 0= scan currently not in vertical blanking portion 1= scan is currently in vertical blanking portion [1] Bit 6: LPEN register full 0= goes to 0 whenever R16 or R17 are read 1= goes 1 when an LPEN strobe occurs Bit 7: not used Rockwell 6545 Bits 0-6: see Rockwell 6545-1 Bit 7: Update Ready 0= register 16 or 17 has been read by the CPU 1= an update strobe has been occurred. Motorola 6845, 6845-1, Hitachi 46505 The status register is not mentioned at all... [1] The Rockwell 6545 docs say that this bit "switches state at end of last displayed rasterline" and "goes to a 0 five character clock times before vertical retrace ends to ensure that critical timings for refresh RAM is met." Register File The following registers are basically the same for all chips (see notes): R0 Horizontal Total (-1) R1 Horizontal Display R2 Horizontal Sync position [1] R4 Vertical total character lines (-1) (7 bit) R5 Vertical total adjust rasterlines (5 bit) R6 Vertical displayed character lines (7 bit) R7 Vertical Sync position (7 bit) [1] R9 Number of rasterlines per characterline (-1) [2] R10 Cursor start rasterline + cursor mode control (5+2 bit) R11 Cursor end rasterline (5 bit) R12 Display start address high (6 bit) [3] R13 Display start address low (8 bit) [3] R14 Cursor address high (6 bit) R15 Cursor address low (8 bit) R16 Lightpen address high (6 bit) R17 Lightpen address low (8 bit) [1] Motorola states that "(Set data) = (Designated Data) - 1", as it is known for R0, R4, and R9 [2] Commodore does not mention the "-1" [3] It is possible to read R12 and R13 on Motorola CRTCs only. All others can only read R14-R17. Reading unused bits where possible reads a "0", which is, however, only explicitly stated in the Commodore docs. The major differences in the register file The following items describe the major register file differences. R3, sync widths Motorola 6845, Hitachi 46505: Bits 0-3: horizontal sync width in character times. Value=0 -> 16 Bits 4-7: unused Commodore 6545-1, Rockwell 6545 and 6545-1, Motorola 6845-1: Bits 0-3: horizontal sync width in character times. Value=0 -> 16 Bits 4-7: vertical sync width in rasterlines. Value=0 -> 16 R8, Mode Control Commodore 6545-1 and Rockwell 6545-1: Bit 0,1: Interlace control value of bits (1/0): x0: non-interlace [Rockwell says "Bit 0 must program to 0"] x1: invalid "do not use" [Rockwell says "not used"] Bit 2: 0 = straight binary addressing 1 = row/column addressing (see below) Bit 3: "Must Program to '0'" Bit 4: Display Enable Skew 0 = no delay 1 = delay Display Enable for one character clock cycle Bit 5: Cursor Enable Skew 0 = no delay 1 = delay Cursor Enable for one character clock cycle Bit 6,7: not used Rockwell 6545: Bits 0,1: Interlace control, see Motorola 6545 Bit 2: Addressing Mode, see Rockwell 6545-1 Bit 3: Refresh RAM access 0= shared memory access 1= transparent memory access Bit 4/5: display enable and cursor skew. See Rockwell 6545-1 Bit 6: Update Strobe (Transparent mode): 0= Pin 34 functions as memory address (RA4) 1= Pin 34 functions as update strobe Bit 7: Update/Read mode (Transparent mode): 0= Update occurs during horizontal and vertical blanking 1= Update interleaves during Phi2 portion of cycle Motorola 6845 and Hitachi 46505 Bit 0,1: Interlace control (see below) value of bits (1/0): x0: non-interlace, normal mode 01: interlace mode 11: interlace and video mode Bit 2-7: not used Motorola 6845-1 Bit 0-3: see Motorola 6845 Bit 4,5: Display Enable Skew value of bits (5/4): 00: no delay 01: delay Display Enable for one character clock cycle 10: delay Display Enable for two character clock cycles 11: not available Bit 6,7: Display Enable Skew value of bits (7/6): 00: no delay 01: delay Cursor Enable for one character clock cycle 10: delay Cursor Enable for two character clock cycles 11: not available What can be learned already from this diagram? The Motorola 6845 (or the Hitachi 46505, but unlikely) was first and defined a basic set of features. Rockwell and Commodore then used the same derivation from the original design, while Motorola developed slightly different features. However, looking at the "must program to 0" entries, it seems Rockwell was not quick enough to implement the interlace modes and thus released an early version as 6545-1, before getting the full 6545 done, with some additional features. Disclaimer All Copyrights are acknowledged. The information here is provided under the terms of the GNU Public License version 2 unless noted otherwise. Return to Homepage Last modified: 2013-11-02 follow Follow my 8-bit tweets on Twitter (In new window) discuss Discuss my site on this 6502.org forum thread (Forum registration required to post) hot! Dive into the retro feeling and build yourself a Micro-PET or a Multi-board Commodore 4032 replica Need more speed? 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