6850 ACIA
                                  =========

+--------+----------------------------+------------------------------+
|        |           Write            |            Read              |
+========+============================+==============================+
| base+0 |          Control           |           Status             |
|        | b7: Enable receive ints    | b7: Interupt Request         |
|        | b6: RTS low/high           | b6: Receive Parity Error     |
|        | b5: Enable transmit ints   | b5: Receive Data Overrun     |
|        |   b6-5=11: Break           | b4: Framing Error            |
|        | b4: 7bit/8bit data         | b3: Clear To Send not present|
|        | b3: 2/1 stop bits          | b2: DCD not present          |
|        |   b4-3=10: No parity       | b1: Transmit Register Empty  |
|        | b2: even/odd parity        | b0: Receive Register Full    |
|        | b1-0: Clock divide 1/16/64 |                              |
|        |   b1-0=11: Reset           |                              |
+--------+----------------------------+------------------------------+
| base+1 |   Transmit Data Register   |    Receive Data Register     |
+========+============================+==============================+
| base+2 |     Baud Rate Control      |                              |
|        | b7: General Purpose Output |                              |
|        | b6: RTS                    |                              |
|        | b5: RxBaud b2              |                              |
|        | b4: RxBaud b1              |                              |
|        | b3: TxBaud b2              |                              |
|        | b2: RxBaud b0              |                              |
|        | b1: TxBaud b1              |                              |
|        | b0: TxBaud b0              |                              |
+--------+----------------------------+------------------------------+

Base  Device
------------------------------------------------------
FC08  M2000 MIDI Port 1, EE MIDI Port, EMR MIDI Port
FC0A  M2000 MIDI Port 2
FC0C  M2000 MIDI Port 3
FC60  Sprow external serial port 1 (COM2)
FC64  Sprow external serial port 2 (COM3)
FC68  Sprow external serial port 3 (COM4)
FC6C  Sprow external serial port 4 (COM5)
FCF0  JGH MIDI Port 1, ETI MIDI Port 1, EE MIDI Port, EMR MIDI Port
FCF2  JGH MIDI Port 2, ETI MIDI Port 2
FCF4  JGH MIDI Port 3
FCF6  JGH MIDI Port 4
FE08  BBC Internal serial port

M2000 MIDI interface
--------------------
Three ports, fully decoded and mapped into &FC08-&FC0D. MIDI requires 8-bit
data 1 stop bit, clock divide by 16, by setting the control register to &15.

EE MIDI interface
------------------
One port, not fully decoded, and appears at every address in &FCxx.
Consequently, it can be accessed as though it is any of the M2000, ETI or
JGH MIDI ports. The clock needs to be set to divide by 16, along with
8-bit data 1 stop bit, by setting the control register to &15.

ETI MIDI interface
------------------
Two ports, fully decoded and mapped into &FCF0-&FCF3. MIDI requires 8-bit
data 1 stop bit, clock divide by 16, by setting the control register to &15.

JGH MIDI interface
------------------
One port, fully decoded and selectably mapped to either &FCF0/1, &FCF2/3,
&FCF4/5 or &FCF6/7. MIDI requires 8-bit data 1 stop bit, clock divide by 16,
by setting the control register to &15.

EMR MIDI interface
------------------
One port, not fully decoded, and appears at every address in &FCxx.
Consequently, it can be accessed as though it is any of the M2000, ETI or
JGH MIDI ports. However, the clock needs to be set to divide by 64, along
with 8-bit data 1 stop bit, by setting the control register to &16.

External additional serial ports
--------------------------------
Fully decoded and selectably mapped to either &FE60-3, &FE64-7, &FE68-B or
&FE6C-F. The clock is normally set to divide by 64, with 8-bit 1 stop bit
and RTS low, by setting the control register to &56

BBC internal serial port
------------------------
Partially decoded and has reflections at &FE08-&FE0F. It should be accessed
at &FE08-&FE09. The clock is normally set to divide by 64, with 8-bit 1 stop
bit and RTS low, by setting the control register to &56