Comparison of Serial Controllers, ACIAs, UARTs ============================================== Data Read/Write Status TxRdy RxRdy Control SetRTS ClrRTS ------------------------------------------------------------------------------ 2681 DUART base+3 base+1 &08 &02 6551 ACIA base+0 base+1 &10 &08 6850 ACIA base+1 base+0 &02 &01 base+0 %x00xxxxx %x10xxxxx Tube base+1 base+0 &40 &80 USB base+0 base+1 &40=0 &80=0 Z80 SIO base+0 base+1 &04 &01 6854 ADLC base+2 base+0 &40 &01 8251 UART base+0 base+1 &01 &01 6402 UART base+0 2681 UART base+3 base+1 &08 &02 2781 UART base+11 base+9 &08 &02 6850 UART ========= +--------+---------------------------+-----------------------------+ | | Write | Read | +========+===========================+=============================+ | base+0 | Control | Status | | | b7: Enable receive ints | b7: Interupt Request | | | b6: RTS low/high/break | b6: Receive Parity Error | | | b5: Enable transmit ints | b5: Receive data overrun | | | b4: 7bit/8bit data | b4: Framing Error | | | b3: 2/1 stop bits | b3: Clear To Send | | | b2: even/odd/no parity | b2: DCD not present | | | b1-0: Clock divide/reset | b1: Transmit Register Empty | | | b6-5=11: Break | b0: Receive Register Full | | | b4-3=10: No parity | | | | b1-0=11: Reset | | +--------+---------------------------+-----------------------------+ | base+1 | Transmit Data Register | Receive Data Register | +========+===========================+=============================+ | base+2 | Baud Rate Control | | | | b7: General Purpose Output| | | | b6: RTS | | | | b5: RxBaud b2 | | | | b4: RxBaud b1 | | | | b3: TxBaud b2 | | | | b2: RxBaud b0 | | | | b1: TxBaud b1 | | | | b0: TxBaud b0 | | +--------+---------------------------+-----------------------------+ 6402 UART ========= +--------+----------------------------+-----------------------------+ | | Write | Read | +========+============================+=============================+ | base+0 | Transmit Data Register | Receive Data Register | +--------+----------------------------+-----------------------------+ Control and Status signals are individual control pins 8251 UART ========= +--------+----------------------------+-----------------------------+ | | Write | Read | +========+============================+=============================+ | base+0 | Transmit Data Register | Receive Data Register | +--------+----------------------------+-----------------------------+ | base+1 | Control Register | Status Register | | | b7: Enter Hunt Mode | b7: Data Set Ready | | | b6: Reset, next is Mode | b6: SYNC/BREAK Detected | | | b5: Request To Send | b5: Framing Error | | | b4: Reset Errors | b4: Data Overrun | | | b3: Send Break | b3: Parity Error | | | b2: Receive Enable | b2: Transmit Empty | | | b1: Data Terminal Ready | b1: Receive Ready | | | b0: Transmit Enable | b0: Transmit Ready | | | | | | | Mode Register (after Reset)| | | | b7-6: Stop bits | | | | b5: Odd/Even Parity | | | | b4: Enable Parity | | | | b3-2: Word Length | | | | b1-0: Clock Divide | | +--------+----------------------------+-----------------------------+ 6854 ADLC ========= +--------+----------------------------+-----------------------------+ | | Write | Read | +========+============================+=============================+ | base+0 | Control Register 1 | Status Register 1 | | | b7: Transmit Reset | b7: Interupt | | | b6: Receive Reset | b6: Transmit Buffer Empty | | | b5: Rx Frame Discontinue | b5: Transmitter Underrun | | | b4: Tx Data Service Req | b4: Clear To Send | | | b3: Rx Data Service Req | b3: Flag Detected | | | b2: Tx Interupt Enable | b2: Loop Status | | | b1: Rx Interupt Enable | b1: Status Register 2 Valid| | | b0: Address Control | b0: Receive Data Present | +--------+----------------------------+-----------------------------+ | base+1 | Control Register 2 | Status Register 2 | | | b7: Request To Send | b7: Receive Data Present | | | b6: Clear Tx Status | b6: Receive Overrun | | | b5: Clear Rx Status | b5: Data Carrier Detect | | | b4: Transmit Last Data | b4: Frame Check Error | | | b3: Frame Complete | b3: Abort Received | | | b2: Idle 0=Flag/1=Idle | b2: Receive Idle | | | b1: 1/2-byte Transfers | b1: Frame Valid | | | b0: Prioritise Status | b0: Address Present | | | | | | | Control Register 3 | | | | b7: Loop/DTR Control | | | | b6: Go Active On Poll | | | | b5: Loop/Nonloop mode | | | | b4: Flag Detect Enable | | | | b3: 01/11 Idle | | | | b2: Address Extend | | | | b1: Extended Control Field| | | | b0: Logical Control Field | | +--------+----------------------------+-----------------------------+ | base+2 | Transmit Data, Frame Cont | | +--------+----------------------------+ Receive Data Register + | base+3 | Transmit Data, Frame End | | +--------+----------------------------+-----------------------------+ Z80 SIO ======= +--------+---------------------------+-----------------------------+ | | Write | Read | +========+===========================+=============================+ | base+0 | Transmit Data Register A | Receive Data Register A | +--------+---------------------------+-----------------------------+ | base+1 | Channel A Control register| Channel A Status Register | | | Control Register 0: | Status Register 0: | | | b6-7: Reset CRCs | b7: Break/CRC valid/Abort | | | b3-5: Various Control | b6: Transmit Underrun | | | b2-0: Register Select | b5: Clear To Send | | | | b4: Not SYNC/Frame Flag | | | Control Register 1: | b3: DCD level | | | b7: Enable WAIT/READY | b2: Transmit Buffer Empty | | | b6: Use WAIT logic | b1: Interupt Pending | | | b5: WAIT on to Tx=0/Rx=1 | b0: Receive Buffer Full | | | b4-3: Rx Interupts | | | | b2: Vectored Interupts | Status Register 1: | | | b1: Tx Interupt Enable | b7: End of Frame | | | b0: Status Int. Enable | b6: Framing Error/CRC Error| | | | b5: Receive Overrun | | | Control Register 2: | b4: Parity Error | | | Interupt Vector Byte | b1-3: Bits in last byte | | | | b0: Transmit Buffer Empty | | | Control Register 3: | | | | b7-6: Word size | Status Register 2: | | | b5: Enable CDC and CTS | Interupt Vector | | | b4: Re-enter hunt mode | | | | b3: Start CRC calculation| | | | b2: Reject invalid addrs | | | | b1: Strip SYNC chars | | | | b0: Enable Rx logic | | | | | | | | Control Register 4: | | | | b7-6: Clock Divide | | | | b5-4: SYNC mode | | | | b3-2: ASYNC mode | | | | b1: Odd/Even Parity | | | | b0: Enable Parity | | | | | | | | Control Register 5: | | | | b7: Enable DTR | | | | b6-5: Tx Word Size | | | | b4: Send Break | | | | b3: Tx Logic Enable | | | | b2: 0=SLDC, 1=CRC-16 | | | | b1: RTS control | | | | b0: CRC on current char | | | | | | | | Control Register 6: | | | | Address/Sync Character 1 | | | | | | | | Control Register 7: | | | | Flag/Sync Character 2 | | +--------+---------------------------+-----------------------------+ | base+2 | Transmit Data Register B | Receive Data Register B | +--------+---------------------------+-----------------------------+ | base+3 | Channel B Control register| Channel B Status Register | +========+===========================+=============================+ 2681 DUART ========== The 2681 DUART is used in the Jafa Electron Serial Interface +=========+============================+==============================+ | | Write | Read | +=========+============================+==============================+ | base+0 | Mode Register A1/B1 | | PORT A | b7: RxRTS control 0=No, 1=Yes | | | b6: RxINT select 0=RdRDY, 1=RxFull | | base+8 | b5: Error mode 0=char, 1=block | | PORT B | b4-3: Parity 00=Yes, 01=Forced, 10=None, 11=Multi| | | b5: Parity 0=Even, 1=Odd | | | b1-0: Character size 00=5, 01=6, 10=7, 11=8 | | | | | | Mode Register A2/B2 | | | b7-6: Channel 00=Normal, 10=Local Loop | | | 01=Echo, 11=Remote Loop | | | b5: TxRTS control 0=No, 1=Yes | | | b4: TxCTS enable 0=No, 1=Yes | | | b3-0: Stop bit 0=0.563 ... F=2.000 | +---------+----------------------------+------------------------------+ | base+1 | Clock Select Register A/B | Status Register A/B | | PORT A | b7-4: Rx baud | b7: Break received | | | b3-0: Tx baud | b6: Receive Framing error | | base+9 | If ACR.b7=0: | b5: Receive Parity Error | | PORT B | 50,110,134,200,300,600, | b4: Receive data overrun | | | 1200,1050,2400,4800, | b3: Transmit Register Empty | | | 7200,9600,38000,timer, | b2: Transmit Register Ready | | | If ACR.b7=1: | b1: Receive Register Full | | | 75,110,134,150,300,600, | b0: Receive Register Ready | | | 1200,2000,2400,4800, | | | | 1800,9600,19200,timer, | | | | TxA 14: IP3x16 15: IP3x1 | | | | RxA 14: IP4x16 15: IP4x1 | | | | TxB 14: IP5x16 15: IP5x1 | | | | RxB 14: IP6x16 15: IP6x1 | | +---------+----------------------------+------------------------------+ | base+2 | Command Register A/B | Reserved (BRG Extend) | | PORT A | b6-b4: Command | | | | 000=null 001=ModeReg 1| | | base+10 | 010=RxReset 011=TxReset | Reserved (1x16x Test) | | PORT B | 100=Reset Error | | | | 101=Reset Break | | | | 110=Start Brk 111=End Brk | | | | b3: Tx Disable | | | | b2: Tx Enable | | | | b1: Rx Disable | | | | b0: Rx Enable | | +---------+----------------------------+------------------------------+ | base+3 | Transmit Data Register A | Receive Data Register A | | PORT A | | | | | | | | base+11 | Transmit Data Register B | Receive Data Register B | | PORT B | | | +=========+============================+==============================+ | base+4 | Aux. Control Register | Input Port Change Register | | | b7: Baud Select | b7: IP3 changed b3: IP3 | | | b6-4: Counter/Timer | b6: IP2 changed b2: IP2 | | | b3: IP3 change enable | b5: IP1 changed b1: IP1 | | | b2: IP2 change enable | b4: IP0 changed b0: IP0 | | | b1: IP1 change enable | | | | b0: IP0 change enable | | +---------+----------------------------+------------------------------+ | base+5 | Interupt Enable Register | Interupt Status Register | | | b7: IntEnable/Input Port b3: Counter Ready | | | b6: BreakB changed b2: BreakA changed | | | b5: RxRDYB/RxFullB b1: RxRDYA/RxFullA | | | b4: TxRDYB b0: TxRDYA | +---------+----------------------------+------------------------------+ | base+6 | Counter/Time Upper Register | +---------+----------------------------+------------------------------+ | base+7 | Counter/Time Lower Register | +=========+============================+==============================+ | base+12 | reserved (scratch) | reserved (scratch) | +---------+----------------------------+------------------------------+ | base+13 | Output Port Config. Reg. | Input Port Register | | | 0=bit set from OPR | b7: always 1 | | | 1=bit set from status | b6-0: Input port | | | b7: TxRDYB | | | | b6: TxRDYA | | | | b5: RxRDYB/RxFullB | | | | b4: RxRDYA/RxFullA | | | | b3: TxCB/RxCB | | | | b2: C/T Output | | | | b1: TxCA/RxCA | | | | b0: TxCA(16x) | | +---------+----------------------------+------------------------------+ | base+14 | Set Output Port Bits | Start Counter | +---------+----------------------------+------------------------------+ | base+15 | Reset Output Port Bits | Stop Counter | +=========+============================+==============================+