Z80 SIO
                                 =======

+--------+----------------------------+-----------------------------+
|        |      Write                 |         Read                |
+========+============================+=============================+
| base+0 |  Transmit Data Register A  |    Receive Data Register A  |
+--------+----------------------------+-----------------------------+
| base+1 |  Channel A Control register|  Channel A Status Register  |
|        | Control Register 0:        | Status Register 0:          |
|        |  b6-7: Reset CRCs          |  b7: Break/CRC valid/Abort  |
|        |  b3-5: Various Control     |  b6: Transmit Underrun      |
|        |  b2-0: Register Select     |  b5: Clear To Send          |
|        |                            |  b4: Not SYNC/Frame Flag    |
|        | Control Register 1:        |  b3: DCD level              |
|        |  b7: Enable WAIT/READY     |  b2: Transmit Buffer Empty  |
|        |  b6: Use WAIT logic        |  b1: Interupt Pending       |
|        |  b5: WAIT on to Tx=0/Rx=1  |  b0: Receive Buffer Full    |
|        |  b4-3: Rx Interupts        |                             |
|        |  b2: Vectored Interupts    | Status Register 1:          |
|        |  b1: Tx Interupt Enable    |  b7: End of Frame           |
|        |  b0: Status Int. Enable    |  b6: Framing Error/CRC Error|
|        |                            |  b5: Receive Overrun        |
|        | Control Register 2:        |  b4: Parity Error           |
|        |  Interupt Vector Byte      |  b1-3: Bits in last byte    |
|        |                            |  b0: Transmit Buffer Empty  |
|        | Control Register 3:        |                             |
|        |  b7-6: Word size           | Status Register 2:          |
|        |  b5: Enable CDC and CTS    |  Interupt Vector            |
|        |  b4: Re-enter hunt mode    |                             |
|        |  b3: Start CRC calculation |                             |
|        |  b2: Reject invalid addrs  |                             |
|        |  b1: Strip SYNC chars      |                             |
|        |  b0: Enable Rx logic       |                             |
|        |                            |                             |
|        | Control Register 4:        |                             |
|        |  b7-6: Clock Divide        |                             |
|        |  b5-4: SYNC mode           |                             |
|        |  b3-2: ASYNC mode          |                             |
|        |  b1: Odd/Even Parity       |                             |
|        |  b0: Enable Parity         |                             |
|        |                            |                             |
|        | Control Register 5:        |                             |
|        |  b7: Enable DTR            |                             |
|        |  b6-5: Tx Word Size        |                             |
|        |  b4: Send Break            |                             |
|        |  b3: Tx Logic Enable       |                             |
|        |  b2: 0=SLDC, 1=CRC-16      |                             |
|        |  b1: RTS control           |                             |
|        |  b0: CRC on current char   |                             |
|        |                            |                             |
|        | Control Register 6:        |                             |
|        |  Address/Sync Character 1  |                             |
|        |                            |                             |
|        | Control Register 7:        |                             |
|        |  Flag/Sync Character 2     |                             |
+--------+----------------------------+-----------------------------+
| base+2 |  Transmit Data Register B  |    Receive Data Register B  |
+--------+----------------------------+-----------------------------+
| base+3 | Channel B Control register |  Channel B Status Register  |
+========+============================+=============================+