http://wwwlehre.dhbw-stuttgart.de/~helbig/os/pdp11/doc/cpu.pdf

0.7 PDP-11/45 and PDP-11/70

0.7.1 Extensions of the Instruction Set.

Instructions that are illegal on the PDP-11/40 might be implemented by other PDP-11
models or by optional hardware extensions.

The MMU in the PDP-11/45/70 supports two mappings per operation mode. One is used for
words addressed by the PC, i.e., instructions, the other for the rest. This feature is
called ”separate I/D space”.

Floating point instructions are offered either by the ”Floating Point Instruction Set”
(FIS), a small extension, or by the ”FP11”, a full blown floating point processor.

The mtps/mfps instructions are only needed by models that cannot access the PSW, and
therefore the PS, via the I/O page.

ass     read                      code           implemented in
--------------------------------------------------------------------------
mfpt    move from processor type  000007         other models
spl     set IPL to m              00023m         PDP-11/45, PDP-11/70
csm     call supervisor mode      0070dd         PDP-11/45, PDP-11/70
tstset  test & set                0072dd         multiprocessor machines
wrtlck  write locked              0073dd         multiprocessor machines
FIS     floating pt. instr. set   075000-075777  optional for PDP-11/40
CIS     commercial instr. set     076000-076777  optional for other models
mtps    move to PS                1064dd         other models
mfpd    move from prev d-space    1065dd         PDP-11/45, PDP-11/70
mtpd    move to prev d-space      1066dd         PDP-11/45, PDP-11/70
mfps    move from PS              1067dd         other models
FP11    floating pt. processor    170000-177777  PDP-11/70, optional for /45