Department of Computer Science

PDP11 Processor Handbook

Instruction Set

Introduction

The PDP11 instruction set offers a wide selection of operations and addressing modes. To save memory space and to simplify the implementation of control and communications applications, the PDP11 instructions allow byte and word addressing in both single- and double-operand formats. By using the double-operand instructions, you can perform several operations with a single instruction. For example, ADD A,B adds the contents of location A to location B, storing the result in location B. Traditional computers would implement this instruction this way:

              LDA A
              ADD B
              STR B

The PDP11 instruction set also contains a full set of conditional branches that eliminate excessive use of jump instructions. PDP11 instructions fall into one of seven categoreis:

Single-Operand - the first part of the word, called the "opcode", specifies the operation; the second part provides information for locating the operand.
Double-Operand - the first part of the word specifies the operation to be performed; the remaining two parts provide information for location two operands.
Branch - the first part of the word specifies the operation to be performed; the second part indicates where the action is to take place in the program.
Jump and Subroutine - these instructions have an opcode and address part, and in the case of JSR, a register for linkage.
Trap - these instructions contain an opcode only. In TRAP and EMT, the low-order byte may be used for function dispatching.
Miscellaneous - HALT, WAIT, and Memory Management.
Condition Code - these instructions set or clear the condition codes.

Single-Operand Instructions

	Mnemonic	Instruction
General
	CLR(B)	clear destination
	COM(B)	1's complement dst
	INC(B)	increment dst
	DEC(B)	decrement dst
	NEG(B)	2's complement negate dst
	NOP	no operation
	TST(B)	test dst
	TSTSET	test dst, set low bit (MICRO/J-11 only)
	WRTLCK	read/lock dst, write/unlock R0 into dst (MICRO/J-11 only)
Shift & Rotate
	ASR(B)	arithmetic shift right
	ASL(B)	arithmetic shift left
	ROR(B)	rotate right
	ROL(B)	rotate left
	SWAB	swap bytes
Multiple Precision
	ADC(B)	add carry
	SBC(B)	subtract carry
	SXT	sign extend

Instruction Format

Single-Operand Instruction Format

Bit 15 indicates word or byte operation.
Bits 14-6 indicate the operation code, which specifies the operation to be performed
Bits 5-0 indicate the 3-bit addressing mode field and the 3-bit general register field. These two fields are referred to as the destination field.

Double-Operand Instructions

	Mnemonic	Instruction
General
	MOV(B)	move source to destination
	ADD	add source to destination
	SUB	subtract source from destination
	CMP(B)	compare source to destination
	ASH	shift arithmetically
	ASHC	arithmetic shift combined
	MUL	multiply
	DIV	divide
Logical
	BIT(B)	bit test
	BIC(B)	bit clear
	BIS(B)	bit set
	XOR	exclusive OR

Instruction Format

Double-Operand Instruction Format

The format of most double-operand instructions, though similar to that of single-operand instructions, has two fields for locating operands. One field is called the source field, the other is called the destination field. Each field is further divided into addressing mode and selected register. Each field is completely independent. The mode and register used by one field may be completely different than the mode and register used by another field.

Bit 15 indicates word or byte operation except when used with opcode 6, in which case it indicates an ADD or SUBtract instruction.
Bits 14-12 indicate the opcode, which specifies the operation to be done.
Bits 11-6 indicate the 3-bit addressing mode field and the 3-bit general register field. These two fields are referred to as the source field.
Bits 5-0 indicate the 3-bit addressing mode field and the 3-bit general register field. These two fields are referred to as the destination field.
Some doubl-operand instructions (ASH, ASHC, MUL, DIV) must have the destination operand only in a register. Bits 15-9 specify the opcode. Bits 8-6 specify the destination register. Bits 5-0 contain the source field. XOR has a similar format, except that the source is in a register specified by bits 8-6, and the destination field is specified by bits 5-0.

Byte Instructions

The PDP11 includes a full complement of instructions that manipulate byte operands. Since all PDP11 addressing is byte-oriented, byte manipulation addressing is straightforward. Byte instructions with autoincrement or autodecrement direct addressing cause the specified register to be modified by one to point to the next byte of data. Byte operations in register mode access the low-order byte of the specified register. These provisions enable the PDP11 to perform as either a word or byte processor. The numbering scheme for word and byte addresses in memory is:

Byte instructions are specified by setting bit 15. Thus, in the case of the MOV instruction, bit 15 is 0; whin bit 15 is set, the mnemonic is MOVB. There are no byte operations for ADD and SUB, i.e., no ADDB or SUBB.

Example:

Symbolic	Octal
CLR	0050DD	Clear Word
CLRB	1050DD	Clear Byte

Branch Instructions

	Mnemonic	Instruction
Branch
	BR	branch (unconditional)
	BNE	branch if not equal (to zero)
	BEQ	branch if equal (to zero)
	BPL	branch if plus
	BMI	branch if minus
	BVC	branch if overflow is clear
	BVS	branch if overflow is set
	BCC	branch if carry is clear
	BCS	branch if carry is set
Signed Conditional Branch
	BGE	branch if greater than or equal (to zero)
	BLT	branch if less than (zero)
	BGT	branch if greater than (zero)
	BLE	branch if less than or equal (to zero)
	SOB	subtract one and branch (if not = 0)
Unsigned Conditional Branch
	BHI	branch if higher
	BLOS	branch if lower to same
	BHIS	branch if higher or same
	BLO	branch if lower

Instruction Format

The high byte (bits 15-8) of the instruction is an opcode specifying the conditions to be tested.
The low byte (bits 7-0) of the instruction is signed offset value in words that determines the new program location if the branch is taken. Thus, program control can be transferred within a range of -128 to +127 words from the updated PC.

Jump and Subroutine Instructions

Mnemonic	Instruction
JMP	jump
JSR	jump to subroutine
RTS	return from subroutine
MARK	facilitates stack clean-up procedures

JSR Instruction Format

Bits 15-9 are always octal 004, the opcode for JSR
Bits 8-6 specify the link register. Any general purpose register may be used in the link, except R6 (SP).
Bits 5-0 designate the destination field that consists of addressing mode and general register fields. This specifies the starting address of the subroutine.
Register R7 (the Program Counter) is frequently used for both the link and the destination. For example, you may use JSR R7, SUBR, which is coded 004767. R7 is the only register that can be used for both the link and destination, the other GPRs cannot. Thus, if the link is R5, any register except R5 can be used for one destination field.

RTS Instruction Format

RTS Instruction Format

The RTS (return from subroutine) instruction uses the link to return control to the main program once the subroutine is finished.

Bits 15-3 always contain octal 00020, which is the opcode for RTS
Bits 2-0 specify any one of the general purpose registers.
The register specified by bits 2-0 must be the same register used as the link between the JSR causing the jump and the RTS returning control.

Traps and Interrupts

Mnemonic	Instruction
EMT	emulator trap
TRAP	trap
BPT	breakpoint trap
IOT	input/output trap
CSM	call to supervisor mode
RTI	return from interrupt
RTT	return from interrupt

The three ways to leave a main program are:

Software exit - the program specifies a jump to some subroutine
Trap exit - internal hardware on a special instruction forces a jump to an error hanling routine
Interrupt exit - external hardware forces a jump to an interrupt service routine

In each case, a jump to another program occurs. Once the latter program has been executed, control is returned to the proper point in the main program.

Miscellaneous Instructions

Mnemonic	Instruction
HALT	halt
WAIT	wait for interrupt
RESET	reset UNIBUS
MTPD	move to previous data space
MTPI	move to previous instruction space
MFPD	move from previous instruction space
MFPI	move from previous instruction space
MTPS	move byte to processor status word
MFPS	move byte from processor status word
MFPT	move from processor type

Note that on the PDP11/70, the four instructions for referencing the previous address space (MTPD, MTPI, MFPD, MFPI) use the General Register set indicated by PSW<11> when they are executed.

Condition Code Operation

Mnemonic	Instruction
CLC, CLV, CLZ, CLN, CCC	clear
SEC, SEV, SEZ, SEN, SCC	set

The four condition code bits are:

N, indicating a negative condition when set to 1
Z, indicating a zero condition when set to 1
V, indicating an overflow condition when set to 1
C, indicating a carry condition when set to 1

These four bits are part of the processor status word (PS). The result of any singal-operand or double-operand instruction affects one or more of the four condition code bits. A new set of condition codes is usually created after execution of each instruction. Some condition codes are not affected by the execution of certain instructions. The CPU may be asked to check the condition codes after execution of an instruction. The condition codes are used by the vairous instructions to check software conditions.

Z bit - Whenever the CPU sees that the result of an instruction is zero, it sets the Z bit. If the result is not zero, it clears the Z bit. There are a number of ways of obtaining a zero result:

Adding two number equal in magnitude but different in sign
Comparing two number of equal value
Using the CLR or BIC instruction

N bit - The CPU looks only at the sign bit of the result. If the sign bit is set, indicating a negative value, the CPU sets the N bit. If the sign bit is clear, indicating a positive value, the the CPU clears the N bit.

C bit - The CPU sets the C bit automatically when the result of an instruction has caused a carry out of the most significant bit of the result. Otherwise, the C bit is cleared. During rotate instructions (ROL and ROR), the C bit forms a buffer between the most significant bit and the least significant bit of the word. A carry of 1 sets the C bit while a carry of 0 clears the C bit. However, there are exceptions. For example:

SUB and CMP set the C bit when there is no carry
INC and DEC do not affect the C bit.
COM always sets the C bit, TST always clears the C bit.

V bit - The V bit is set to indicate that an overflow condition exists. An overflow means that the result of an instruction is too large to be placed in the destination. The harware uses one of two methods to check for an overflow condition.

One way is for the CPU to test for a change of sign.

When using single-operand instructions, such as INC, DEC, or NEG, a change of sign indicates an overflow condition.
When using double-operand instruction, such as ADD, SUB, or CMP, in which both the source and destination have like signs, a change of sign in the result indicates an overflow condition.

Another method used by the CPU is to test the N bit and C bit when dealing with shift and rotate instructions.

If only the N bit is set, an overflow exists.
If only the C bit is set, an overflow exists.
If both the N and C bits are set, there is no overflow condition.

More than one condition code can be set by a particular instruction. For example, both a carry and an overflow condition may exist after instruction execution.

Instruction Format

Condition Code Operators' Format

The format of the condition code operators is:

Bits 15-5 - the opcode
Bit 4 - the "operator" which indicates set or clear with the values 1 and 0 respectively. If set, any selected bit is set; if clear, any selected bit is cleared.
Bits 3-0 - the mask field. Each of these bits corresponds to one of the four condition code bits. When one of these bits is set, then the corresponding condition code bit is set or cleared depending on the state of the "operator" (bit 4).

Examples

The following examples and explanations illustrate the use of the various types of instructions in a program.

Single-Operand Instruction Example

This routine uses a tally to control a loop, which clears out a specific block of memory. The routine has been set up to clear 30(base 8) byte locatations beginning at memory address 600.

INIT: MOV #600, R0
MOV #30, R1
LOOP: CLRB (R0)+
DEC R1
BNE LOOP
HALT
Program Description:

The CLRB (R0)+ instruction clears the content of the location specified by R0 and increments R0.
R0 is the pointer.
Because the autoincrement addressing mode is used, the pointer automatically moves to the next memory location after execution of the CLRB instruction.
Register R1 indicates the number of locations to be cleared and is, therefore, a counter. Counting is performed by the DEC R1 instruction. Each time a location is cleared, it is counted by decrementing R1.
The Branch if Not Zero, BNE, instruction checks for done. If the counter is not zero, the program branches back to clear another location. If the counter is zero, indicating done, then the program halts.

Double-Operand Instruction Example

This routine moves characters to be printed from location 600 into a print buffer area in memory.

INIT MOV #600, R0 ; set up source address
MOV #prtbuf, R1 ; set up destination address
MOV #76, R2 ; set up loop count
START MOVB (R0)+, (R1)+ ; move one character
; and increment
; both source and
; destination addresses
DEC R2 ; decrement count by one
BNE START ; loop back if
HALT decremented counter is not
; equal to zero
Program Description:

MOV is the instruction normally used to set up the initial conditions. Here, the first MOV places the starting address (600) into R0, which will be used as a pointer. The second MOV places the starting address of the print buffer int R1. The third MOV sets up R2 as a counter by loading the desired number of locations (76) to be printed.
The MOVB instruction moves a byte of data to the printer buffer. The data comes from the location specified by RO. The pointers R0 and R1 are then incremented to point to the next sequential location.
The counter (R2) is then decremented to indicate one byte has been transferred.
The program then checks the loops for done with the BNE instruction. If the counter has not reached zero, indicating more transfers must take place, then the BNE causes a branch back to START and the program continues.
When the counter (R2) reaches zero, indicating all data have been transferred, the branch does not occur and the program halts.

Branch Instruction Example

NOTE: branch instruction offsets are limited to the range of +177(base 8) to -200(base 8) words.

A payroll program has set up a series of words to identify each employee by his badge number. The high byte of the word contains the employee's badge number, the low byte contains an octal number ranging from 0 to 13 which represents his salary. These numbers represent steps within three wage classes to identify which employees are paid weekly, monthly, or quarterly. It is time to make out weekly paychecks. Unfortuneately, employee information has been stored in a random order. The problem is to extract the names of only those employees who receive a weekly paycheck. Employee payroll numbers are assigned as follows: 0 to 3 - Wage Class I (weekly), 4 to 7 - Wage Class II (monthly), 10 to 13 - Wage class III (quarterly).

600 is the starting address of memory block containing the employee payroll information. 1264 is the final address of this data area. The following program searches through the data area and finds all numbers representing Wage Class I, and, each time an appropriate number is found, stores the employee's badge number (just the high byte) on a Last-in/First-out stack which begins at location 4000.

INIT MOV #600, R0
MOV #4000, R1

START CMPB(R0), #3

BHI CONT

STACK MOVB (R0), -(R1)

CONT INC R0

CMP #1264, R0

BHIS START

Program Description:

R0 becomes the address pointer, R1 the stack pointer.
Compare the contents of the first low byte with the number 3 and go to the first high byte.
If the number is more than 3, branch to continue.
If no branch occurs, it indicates that the number is 3 or less. Therefore, move the high byte containing the employee's number onto the stack as indicated by stack pointer R1.
R0 is advanced to the next low byte.
If the last address has not been examined (1264), this instruction produces a result equal to or greater than zero.
If the result is equal to or greater than zero, examine the next memory location.

Summary of PDP11 Instruction Set

Basic PDP11 Instruction Set

ADC	BIT	COM	ROL
ADCB	BITB	COMB	ROLB
ADD	BLE	DEC	ROR
ASL	BLO	DECB	RORB
ASLB	BLOS	EMT	RTI
ASR	BLT	HALT	RTS
ASRB	BMI	INC	RTT
BCC	BNE	INCB	SBC
BCS	BPL	IOT	SBCB
BEQ	BPT	JMP	SCC,SEN,
			SEZ,
			SEV,SEC
BGE	BR	JSR	SOB
BGT	BVC	MARK	SUB
BHI	BVS	MOV	SXT
BHIS	CLR	MOVB	SWAB
BIC	CLRB	NEG	TRAP
BICB	CCC, CLN	NEGBB	TST
	CLZ,
	CLV, CLC
BIS	CMP	NOP	TSTB
BISB	CMPB	RESET	XOR
			WAIT

The basic PDP11 instructions are standard on:

MICRO/T-11
MICRO/J-11
LSI-11/2
FALCON SBC-11/21 (except for MARK instruction)
MICRO/PDP11
PDP11/23 PLUS
PDP11/24
PDP11/44

The PDP11 compatibility mode on VAX-11 implements all basic PDP11 instructions except: MARK, RESET, TRAP, WAIT, BPT, EMT, IOT, and HALT.

CSM
Available on MICRO/J-11 and PDP11/44 only.

MFPD, MFPI, MTPD, MTPI
Available on the MICRO/J-11, LSI-11/23, MICRO/PDP11, PDP11/23-PLUS, PDP11/24, PDP11/44, and VAX-11 compatibility mode.

MFPS, MTPS
Available on the MICRO/T-11, MICRO/J-11, LSI-11/2, FALCON SBC-11/21, LSI-11/23, MICRO/PDP11, PDP11/23-PLUS, and PADP-11/24.

MFPT
Available on the MICRO/T-11, MICRO/J-11, FALCON SBC-11/21, LSI-11/23, MICRO/PDP11, PDP11/23-PLUS, PDP11/24, and PDP11/44.

SPL
Available on MICRO/J-11 and PDP-1/44 only.

TSTSET, WRTLCK
Available on MICRO/J-11 only.

Extended Integer Instructions (EIS)
ASH
ASHC
DIV
MUL

EIS is standard on:

MICRO/PDP11
PDP11/23 PLUS
PDP11/24
PDP11/44
VAX-11 compatibility mode

EIS is also available as an option on the LSI-11/2

LSI-11
PDP11/35 & 40

Floating Instruction set (FIS)
FADD
FSUB
FMUL
FDIV

FIS is unique to:

LSI-11
PDP11/35 & 40

Don S. Bidulock
Department of Computer Science
University of Calgary
Calgary, Alberta
Canada T2N 1N4
Phone: 403 220-7689 Fax: 403 284-4707
email: dsb@cpsc.ucalgary.ca

INIT:	MOV #600, R0 MOV #30, R1
LOOP:	CLRB (R0)+ DEC R1 BNE LOOP HALT

INIT	MOV #600, R0	; set up source address
	MOV #prtbuf, R1	; set up destination address
	MOV #76, R2	; set up loop count
START	MOVB (R0)+, (R1)+	; move one character
		; and increment
		; both source and
		; destination addresses
	DEC R2	; decrement count by one
	BNE START	; loop back if
	HALT	decremented counter is not
		; equal to zero

INIT	MOV #600, R0
	MOV #4000, R1

START	CMPB(R0), #3


	BHI CONT

STACK	MOVB (R0), -(R1)

CONT	INC R0

	CMP #1264, R0

	BHIS START