Full Rabbit Opcode List ======================= File: Docs.Comp.Rabbit.OpList - Update: 0.11 Author: J.G.Harston - Date: 12-06-2005 nn nn DD nn CB nn FD CB dd nn ED nn ----------------------------------------------------------------------------------- 00 NOP - RLC B - - 01 LD BC,&0000 - RLC C - - 02 LD (BC),A - RLC D - - 03 INC BC - RLC E - - 04 INC B - RLC H - - 05 DEC B - RLC L - - 06 LD B,&00 - RLC (HL) RLC (IY+d) - 07 RLCA - RLC A - - 08 EX AF,AF' - RRC B - - 09 ADD HL,BC ADD IX,BC RRC C - - 0A LD A,(BC) - RRC D - - 0B DEC BC - RRC E - - 0C INC C - RRC H - - 0D DEC C - RRC L - - 0E LD C,&00 - RRC (HL) RRC (IY+d) - 0F RRCA - RRC A - - 10 DJNZ &4546 - RL B - - 11 LD DE,&0000 - RL C - - 12 LD (DE),A - RL D - - 13 INC DE - RL E - - 14 INC D - RL H - - 15 DEC D - RL L - - 16 LD D,&00 - RL (HL) RL (IY+d) - 17 RLA - RL A - - 18 JR &4546 - RR B - - 19 ADD HL,DE ADD IX,DE RR C - - 1A LD A,(DE) - RR D - - 1B DEC DE - RR E - - 1C INC E - RR H - - 1D DEC E - RR L - - 1E LD E,&00 - RR (HL) RR (IY+d) - 1F RRA - RR A - - 20 JR NZ,disp - SLA B - - 21 LD HL,&0000 LD IX,&0000 SLA C - - 22 LD (&0000),HL LD (&0000),IX SLA D - - 23 INC HL INC IX SLA E - - 24 INC H - SLA H - - 25 DEC H - SLA L - - 26 LD H,&00 - SLA (HL) SLA (IY+d) - 27 ADD SP,&00 - SLA A - - 28 JR Z,disp - SRA B - - 29 ADD HL,HL ADD IX,IX SRA C - - 2A LD HL,(&0000) LD IX,(&0000) SRA D - - 2B DEC HL DEC IX SRA E - - 2C INC L - SRA H - - 2D DEC L - SRA L - - 2E LD L,&00 - SRA (HL) SRA (IY+d) - 2F CPL - SRA A - - 30 JR NC,disp - - - - 31 LD SP,&0000 - - - - 32 LD (&0000),A - - - - 33 INC SP - - - - 34 INC (HL) INC (IX+d) - - - 35 DEC (HL) DEC (IX+d) - - - 36 LD (HL),&00 LD (IX+d),&00 - - - 37 SCF - - - - 38 JR C,disp - SRL B - - 39 ADD HL,SP ADD IX,SP SRL C - - 3A LD A,(&0000) - SRL D - - 3B DEC SP - SRL E - - 3C INC A - SRL H - - 3D DEC A - SRL L - - 3E LD A,&00 - SRL (HL) SRL (IY+d) - 3F CCF - SRL A - - 40 LD B,B - BIT 0,B - - 41 LD B,C - BIT 0,C - LD BC',DE 42 LD B,D - BIT 0,D - SBC HL,BC 43 LD B,E - BIT 0,E - LD (&0000),BC 44 LD B,H - BIT 0,H - NEG 45 LD B,L - BIT 0,L - LRET 46 LD B,(HL) LD B,(IX+d) BIT 0,(HL) BIT 0,(IY+d) IPSET 0 47 LD B,A - BIT 0,A - LD EIR,A 48 LD C,B - BIT 1,B - - 49 LD C,C - BIT 1,C - LD BC',BC 4A LD C,D - BIT 1,D - ADC HL,BC 4B LD C,E - BIT 1,E - LD BC,(&0000) 4C LD C,H - BIT 1,H - - 4D LD C,L - BIT 1,L - RETI 4E LD C,(HL) LD C,(IX+d) BIT 1,(HL) BIT 1,(IY+d) IPSET 2 4F LD C,A - BIT 1,A - LD IIR,A 50 LD D,B - BIT 2,B - - 51 LD D,C - BIT 2,C - LD DE',DE 52 LD D,D - BIT 2,D - SBC HL,DE 53 LD D,E - BIT 2,E - LD (&0000),DE 54 LD D,H - BIT 2,H - EX (SP),HL 55 LD D,L - BIT 2,L - - 56 LD D,(HL) LD D,(IX+d) BIT 2,(HL) BIT 2,(IY+d) IPSET 1 57 LD D,A - BIT 2,A - LD A,EIR 58 LD E,B - BIT 3,B - - 59 LD E,C - BIT 3,C - LD DE',BC 5A LD E,D - BIT 3,D - ADC HL,DE 5B LD E,E - BIT 3,E - LD DE,(&0000) 5C LD E,H - BIT 3,H - - 5D LD E,L - BIT 3,L - IPRES 5E LD E,(HL) LD E,(IX+d) BIT 3,(HL) BIT 3,(IY+d) IPSET 3 5F LD E,A - BIT 3,A - LD A,IIR 60 LD H,B - BIT 4,B - - 61 LD H,C - BIT 4,C - LD HL',DE 62 LD H,D - BIT 4,D - SBC HL,HL 63 LD H,E - BIT 4,E - LD (&0000),HL 64 LD H,H LDP (IX),HL BIT 4,H - LDP (HL),HL 65 LD H,L LDP (&0000),IX BIT 4,L - LDP (&0000),HL 66 LD H,(HL) LD H,(IX+d) BIT 4,(HL) BIT 4,(IY+d) - 67 LD H,A - BIT 4,A - LD XPC,A 68 LD L,B - BIT 5,B - - 69 LD L,C - BIT 5,C - LD HL',BC 6A LD L,D - BIT 5,D - ADC HL,HL 6B LD L,E - BIT 5,E - LD HL,(&0000) 6C LD L,H LDP HL,(IX) BIT 5,H - LDP HL,(HL) 6D LD L,L LDP IX,(&0000) BIT 5,L - LDP HL,(&0000) 6E LD L,(HL) LD L,(IX+d) BIT 5,(HL) BIT 5,(IY+d) - 6F LD L,A - BIT 5,A - - 70 LD (HL),B LD (IX+d),B BIT 6,B - - 71 LD (HL),C LD (IX+d),C BIT 6,C - LD AF',DE 72 LD (HL),D LD (IX+d),D BIT 6,D - SBC HL,SP 73 LD (HL),E LD (IX+d),E BIT 6,E - LD (&0000),SP 74 LD (HL),H LD (IX+d),H BIT 6,H - - 75 LD (HL),L LD (IX+d),L BIT 6,L - - 76 ALTD - BIT 6,(HL) BIT 6,(IY+d) PUSH IP 76 E3 EX DE',HL' 76 E3 EX DE,HL' 77 LD (HL),A LD (IX+d),A BIT 6,A - LD A,XPC 78 LD A,B - BIT 7,B - - 79 LD A,C - BIT 7,C - LD AF',BC 7A LD A,D - BIT 7,D - ADC HL,SP 7B LD A,E - BIT 7,E - LD SP,(&0000) 7C LD A,H LD HL,IX BIT 7,H - - 7D LD A,L LD IX,HL BIT 7,L - - 7E LD A,(HL) LD A,(IX+d) BIT 7,(HL) BIT 7,(IY+d) POP IP 7F LD A,A - BIT 7,A - - 80 ADD A,B - RES 0,B - - 81 ADD A,C - RES 0,C - - 82 ADD A,D - RES 0,D - - 83 ADD A,E - RES 0,E - - 84 ADD A,H - RES 0,H - - 85 ADD A,L - RES 0,L - - 86 ADD A,(HL) ADD A,(IX+d) RES 0,(HL) RES 0,(IY+d) - 87 ADD A,A - RES 0,A - - 88 ADC A,B - RES 1,B - - 89 ADC A,C - RES 1,C - - 8A ADC A,D - RES 1,D - - 8B ADC A,E - RES 1,E - - 8C ADC A,H - RES 1,H - - 8D ADC A,L - RES 1,L - - 8E ADC A,(HL) ADC A,(IX+d) RES 1,(HL) RES 1,(IY+d) - 8F ADC A,A - RES 1,A - - 90 SUB A,B - RES 2,B - - 91 SUB A,C - RES 2,C - - 92 SUB A,D - RES 2,D - - 93 SUB A,E - RES 2,E - - 94 SUB A,H - RES 2,H - - 95 SUB A,L - RES 2,L - - 96 SUB A,(HL) SUB A,(IX+d) RES 2,(HL) RES 2,(IY+d) - 97 SUB A,A - RES 2,A - - 98 SBC A,B - RES 3,B - - 99 SBC A,C - RES 3,C - - 9A SBC A,D - RES 3,D - - 9B SBC A,E - RES 3,E - - 9C SBC A,H - RES 3,H - - 9D SBC A,L - RES 3,L - - 9E SBC A,(HL) SBC A,(IX+d) RES 3,(HL) RES 3,(IY+d) - 9F SBC A,A - RES 3,A - - A0 AND B - RES 4,B - LDI A1 AND C - RES 4,C - - A2 AND D - RES 4,D - - A3 AND E - RES 4,E - - A4 AND H - RES 4,H - - A5 AND L - RES 4,L - - A6 AND (HL) AND (IX+d) RES 4,(HL) RES 4,(IY+d) - A7 AND A - RES 4,A - - A8 XOR B - RES 5,B - LDD A9 XOR C - RES 5,C - - AA XOR D - RES 5,D - - AB XOR E - RES 5,E - - AC XOR H - RES 5,H - - AD XOR L - RES 5,L - - AE XOR (HL) XOR (IX+d) RES 5,(HL) RES 5,(IY+d) - AF XOR A - RES 5,A - - B0 OR B - RES 6,B - LDIR B1 OR C - RES 6,C - - B2 OR D - RES 6,D - - B3 OR E - RES 6,E - - B4 OR H - RES 6,H - - B5 OR L - RES 6,L - - B6 OR (HL) OR (IX+d) RES 6,(HL) RES 6,(IY+d) - B7 OR A - RES 6,A - - B8 CP B - RES 7,B - LDDR B9 CP C - RES 7,C - - BA CP D - RES 7,D - - BB CP E - RES 7,E - - BC CP H - RES 7,H - - BD CP L - RES 7,L - - BE CP (HL) CP (IX+d) RES 7,(HL) RES 7,(IY+d) - BF CP A - RES 7,A - - C0 RET NZ - SET 0,B - - C1 POP BC - SET 0,C - - C2 JP NZ,&0000 - SET 0,D - - C3 JP &0000 - SET 0,E - - C4 CALL NZ,&0000 LD IX,(SP+d) SET 0,H - - C5 PUSH BC - SET 0,L - - C6 ADD A,&00 - SET 0,(HL) SET 0,(IY+d) - C7 LJP &00,&0000 - SET 0,A - - C8 RET Z - SET 1,B - - C9 RET - SET 1,C - - CA JP Z,&0000 - SET 1,D - - CB **** CB **** **** CB **** SET 1,E - - CC BOOL HL BOOL IX SET 1,H - - CD CALL &0000 - SET 1,L - - CE ADC A,&00 - SET 1,(HL) SET 1,(IY+d) - CF LCALL &00,&0000 - SET 1,A - - D0 RET NC - SET 2,B - - D1 POP DE - SET 2,C - - D2 JP NC,&0000 - SET 2,D - - D3 IOI - SET 2,E - - D4 LD (SP+d),HL LD (SP+d),IX SET 2,H - - D5 PUSH DE - SET 2,L - - D6 SUB A,&00 - SET 2,(HL) SET 2,(IY+d) - D7 RST &10 - SET 2,A - - D8 RET C - SET 3,B - - D9 EXX - SET 3,C - - DA JP C,&0000 - SET 3,D - - DB IOE - SET 3,E - - DC AND HL,DE AND IX,DE SET 3,H - - DD **** DD **** - SET 3,L - - DE SBC A,&00 - SET 3,(HL) SET 3,(IY+d) - DF RST &18 - SET 3,A - - E0 RET PO - SET 4,B - - E1 POP HL POP IX SET 4,C - - E2 JP PO,&0000 - SET 4,D - - E3 EX DE',HL EX (SP),IX SET 4,E - - E4 LD HL,(IX+d) LD HL,(IX+d) SET 4,H - - E5 PUSH HL PUSH IX SET 4,L - - E6 AND &00 - SET 4,(HL) SET 4,(IY+d) - E7 RST &20 - SET 4,A - - E8 RET PE - SET 5,B - - E9 JP (HL) JP (IX) SET 5,C - - EA JP PE,&0000 - SET 5,D - - EB EX DE,HL - SET 5,E - - EC OR HL,DE OR IX,DE SET 5,H - - ED **** ED **** - SET 5,L - - EE XOR &00 - SET 5,(HL) SET 5,(IY+d) - EF RST &28 - SET 5,A - - F0 RET P - SET 6,B - - F1 POP AF - SET 6,C - - F2 JP P,&0000 - SET 6,D - - F3 RL DE - SET 6,E - - F4 LD (IX+d),HL LD (IX+d),HL SET 6,H - - F5 PUSH AF - SET 6,L - - F6 OR &00 - SET 6,(HL) SET 6,(IY+d) - F7 MUL - SET 6,A - - F8 RET M - SET 7,B - - F9 LD SP,HL LD SP,IX SET 7,C - - FA JP M,&0000 - SET 7,D - - FB RR DE - SET 7,E - - FC RR HL RR IX SET 7,H - - FD **** FD **** - SET 7,L - - FE CP &00 - SET 7,(HL) SET 7,(IY+d) - FF RST &38 - SET 7,A - - Notes on index registers ------------------------ Where DD and IX are mentioned, FD and IY may be substituted and vis versa. If a DD or FD opcode prefixes an instruction that does not use the HL register, then the DD or FD opcode acts as a NOP and the base instruction is executed. For example, DD FF does a RST &38. The Rabbit does not implement access to the high and low halves of the index registers, for instance LD A,IXL or RLC IYH. A shift or bit operation on an indexed byte in memory is done by prefixing a CB opcode refering to (HL) with DD or FD to specify (IX+n) or (IY+n). If the CB opcode does not refer to (HL), the DD of FD prefix is executed as a NOP. Notes on ED opcodes ------------------- Unimplemented ED Opcodes execute as NOPs that increment the R register by 2.