Date   : Mon, 05 Nov 2012 23:06:49 +0000
From   : percy.p.person@... (Ed Spittles)
Subject: 6502 timing and zero-page instructions

On 5 November 2012 20:19, Jules Richardson <jules.richardson99@...>
 wrote:

>
> Hmm, so potentially PC might be incremented twice in a single cycle:
>
>    cycle0: increment PC if previous instruction didn't modify PC directly
>            and previous instruction had an operand
>            fetch opcode
>            increment PC only if opcode has an operand
>
>    cycle1: fetch operand
>            increment PC only if operand takes 2 bytes
>
>    cycle2: fetch operand
>
>    ...
>
> ?
>

Hmm, I think it has to be more like

cycle 0: fetch opcode, increment PC

cycle 1: increment PC unless we need no operand.  Read memory anyway.

cycle 2: depends on the opcode.  Could be a fetch of the next one.

That is, I think we always increment on a fetch (because we have no idea
what we're doing) and we always read a potential operand (because at the
start of the cycle we still don't know what we're doing), but during the
operand cycle there's time to have a quick look at the opcode and decide
whether or not to increment the PC.  This is probably a critical timing
path.  The fact that the PC is a 16-bit increment is also probably a
critical timing path, but I don't know if the two paths occupy the same
cycle.

Cheers
Ed