Date   : Thu, 05 Feb 2004 18:02:21 +0100 (GMT)
From   : Johan Heuseveldt <johan@...>
Subject: Re: IDE Interface for BBC

Hi Jonathan,

On Thu 05 Feb, Jonathan Graham Harston wrote:
> Sprow <info@...> wrote:
> > Jonathan Graham Harston <jgh@...> wrote:

> > > Latest update...
> > >  Well, it's still not working.
> > 
> > Thank goodness me "Told you so" tshirt is back from the laundry (see my
> > reply with message id <4c71957ea1info@...>).
> > 
> > > Any suggestions?
> > 
> > Why not just generate the strobes which you require: the 1MHz bus has
> > everything you should need, RnW and a reference clock, infact this is
> > exactly how the disc interface on the main board does it - the 8271 being
> > an Intel chip has Intel strobes,
>  
> That's exactly what the interface does.  Check the schematic at
> http://www.mdfs.net/Info/Comp/BBC/Hardware/IDE
> It's just that it doesn't do what the specs say it should do.  I'm tempted
> to put together the one-chip Spectrum IDE interface and check that my
> brain isn't melting.

Indeed this afternoon I cecked out your drawings.

It's all very long ago I did some designing stuff, but never got get any
further then the drwawing board, because I was redesigning part after
part, when I discovered new details from somewhere.

Looking in more detail at your drawings, and your latest message about change
the timing of ~RD and ~WR: IIRC from ages ago, there should be more time
between the chip select signals and  ~RD and ~WR. You use the clean-up logic
or directly some clock to make one of the CS signals. But this is not done at
the Intel 8271 FDC contoleer; it comes directly from the address lines.

Again, IIRC, it is in many cases not an issue to have spikes on the CS
inputs at those 82xx devices. The important thing is /enough/ time between
the last stable transition of CS, and the next edge of ~RD/~WR. In using some
clean-up circuitry as you do, I have the feeling there is not enough such
time because chip select start on clock phase two, almost at the same time
with as ~RD and ~WR.

Looking at the BBC drawing for the 8271, the ~RD and ~WR are synchronised to
clock phase two, but the CS are as early as possible by coming directly from
decoding logic /without/ any synchronising, so can have many spikes, yes, but
also has a lot of time to stabilize, and also lots of time before ~RD and ~WR
are going active low, because CS is generated somewhere in the first half of
clock phase 1!
(I hope you see my point; English is not my native language)

Well, that's the impression occuring to me many many years ago. So, I could
be completely wrong, but perhaps it's something valuable in your further
efforts. I /do/ hope so!

Otherwise just ignore me!

greetings from the Netherlands,
johan

-- 
Johan Heuseveldt <johan@...              >
  aka  waarland

  The best place is a Riscy place
 
People who can most afford to pay rent build equity.