Date   : Mon, 24 May 2004 09:36:23 +0100
From   : Richard Gellman <splodge@...>
Subject: Re: Tube / Master Coprocessor question

Sprow wrote:

>In article <40B120C0.6010807@...>,
>   Richard Gellman <splodge@...> wrote:
>  
>
>>The tube is an asynchronous dual CPU interface. Whats actually happening 
>>is two CPUs running as two independnt systems, with a chip inbetween 
>>(The TUBE, found typically in the second processor box)
>>    
>>
>
>The Tube, as you point out, is the interface specification, not the name of
>the chip.
>  
>
The Acorn docs refer to this chip as the TUBE ULA. This for me at least 
indicates that the chip is referred as the TUBE as well as the interface 
between CPUs.

>>Note that contrary to the expected behavior, the data is not 
>>signalled by interrupts.
>>    
>>
>
>I'd have to disagree there. A cursory disassembly of the IRQ handler shows
>that messaging from the IO processor to the 2nd processor is done
>exclusively with interrupts, and the high speed block data transfers with
>NMIs.
>  
>
Note aftwards I said "almost" all transfers :) Yes there are some that 
occur under NMIs, but these are used primarily for disk/network access, 
not for housekeeping processes. The parasite side is signalled by IRQ, 
but only on register 1, which is used by the IO processor in the 
host->parasite direction to request attention from the parasite OS.

Note that the specification on the TUBE interface details an IRQ on 
Register 4 to the host. While the chip supports this operation, *most* 
2nd Processor boards do *not* connect the IRQ line to the host. For this 
reason, there isn't (or shouldnt be) any code on the host side to hand 
TUBE interrupts.

As I said, almost all transfers are done under polling :)

>Maybe you were talking about the host not the parasite?
>Sprow.
>
>  
>
-- Richard