<< Previous Message Main Index Next Message >>
<< Previous Message in Thread This Month Next Message in Thread >>
Date   : Sun, 30 Jan 2005 17:26:01 +0000
From   : jgh@... (Jonathan Graham Harston)
Subject: Re: Video ULA shenanigans

Richard_Talbot-Watkins@... wrote:
> rupture' about 3 years ago).  I'd always taken the algorithm in the AUG
> for calculating Mode 7 CRTC addresses at face value, rather than
> actually looking at what it was doing, probably because I'd never had
> any need to scroll a Mode 7 screen.
> 
> So, just looking at the Mode 7 address calculation for a moment:
> 
> R12 = (address.hi - &74) EOR &20
> R13 = (address.lo)
> 
> Some questions:
> 
> * Does this mean it's possible to set *any* character cell in a Mode 7
> screen as the start address and achieve character-by-character horizontal
> scrolling?  I never tried it...
 
Yes, any character cell in &7C00-&7FFF. When MA13 is set by the
EOR &20, this selects output from the 5050 and changes the address
range strobed by the 6845 CRTC to be %011111a9a8a7a6a5a4a3a2a1a0,
that is, addresses based at &7C00 and with offset from 0 to 1023.
 
> * Subtracting &74 seems bizarre to me.  But nonetheless maybe
> implies that memory in the range &7400..&7FFF can be addressed
 
It is bizarre, as the hardware only addresses &7C00-&7FFF. You only
need to get the offset from &7C00 and make sure MA13 is set, so the
above calculation could just as well be:
 
  R12=(address.hi - &7C) OR &20
  R13=(address.lo)
 
It doesn't matter what MA10-MA12 are set to, as they are ignored.
You could just as well use R12=address.hi AND &03. The only need
for them to be set is that the cursor is displayed when the display
address matches the cursor address. The MOS sets the cursor address
using the -&74 EOR &20 method, so the cursor is only visible if R12
is set between &28 and &2C.
 
> in Mode 7.  Is this true? What is stopping us from setting a 64
> row screen with 4 scanlines per row (in 'chunky' Mode 2) and
> setting a start address of &7800?
 
You can't set a start address outside &7C00-&7FFF as the top 5 bits
are all held high. Try FOR A%=&20 to &3F:V.23;12,A%;0;0;0:B%=GET:NEXT
and watch the screen scroll the the same 1K all the time. On oddity
that occurs is when the CRTC address wraps the screen past an area
with MA13=0 and with MA13=1. Setting R12 to &3E tries to display the
top of the screen in non-Teletext and the bottom in Teletext. You get
strange breakage as the video ULA swiches from non-Teletext to
Teletext halfway down the screen.
 
You can changes the displayed width with R1 and, yes, the width
changes appropriately. However, as the CRTC can only access the
top 1K in MODE 7, setting a wider screen repeats the display.
Setting R1 to less than 4 gives a blank display, possibly because
of the character fetch delay means that not enough characters have
been fetched to start a line before the next line is started.
 
Setting R1 larger than about 48 wraps lines off the righthand side
of the screen, larger than about 56 and they start coming back on the
lefthand side.  Setting to 64 or more confuses the CRTC and breaks
up the display as the displayed width is then greater than the total
width.
 
You can change the number of displayed lines in R6. Setting it to 26
will, yes, give 26 lines of teletext charaters, but after the first
24 characters is wraps around back to the start of MODE 7 screen
memory and displays the next 16 characters as a repeat of the first
16 on the first line.
 
You can display up to 27 or 28 lines, but of course, they will only
be repeated what is in memory elsewhere on the screen.
 
Changing the number of pixel-lines per character from 18 in R9 just
breaks up the display, slicing bits off each character row.
 
> Combining R12 and R13 to a 14-bit register, we get:
> bits 0-11: address
> bit 12: unknown
> bit 13: addressing mode select (0 = normal, 1 = teletext style)
> So it appears when bit 13 is clear, then bits 0-11 are mapped to address
> lines A3-A14 - easy. When bit 13 is set, it seems less obvious... it
> looks as if bits 0-9 are mapped to address lines A0-A9 (to cover a full
> Teletext-sized screen), and then maybe the remaining lines A10-A14 are
> hardwired appropriately,
 
Yep, that's about right:
 
Memory     non-Teletext       Teletext
Address    CRTC Address     CRTC Address
                            RA0 ignored
                            RA1 ignored
                            RA2 ignored
                            RA3 ignored
                            RA4 ignored
  A0         RA0                MA0
  A1         RA1                MA1
  A2         RA2                MA2
             RA3->blank line    MA3
             RA4 ignored
  A3         MA0                MA3
  A4         MA1                MA4
  A5         MA2                MA5
  A6         MA3                MA6
  A7         MA4                MA7
  A8         MA5                MA8
  A9         MA6                MA9
  A10        MA7                 1
  A11        MA8                 1
  A12        MA9                 1
  A13        MA10                1
  A14        MA11                1
  A15         0                  0
             MA12->wrapround   MA10/11/12 ignored
             MA13=0            MA13=1
 
I'm sure I read somewhere years ago about a later version of the
6845 that used a full 8-bit R12, giving MA0-MA15, giving access
to four times as much screen memory. With RA0-RA4 and MA0-MA15
fully used, that would give access to 2048K of screen memory.
 
> don't understand why it seems necessary to also set bit 11, as is always
> the case for normal Mode 7-range addresses.  What happens if it is not set?
> Can we *really* start a Mode 7 screen at an address lower than &7C00?
 
If MA11 is not set, the cursor is not displayed as the cursor address
never matches the display address.
 
> And also, does anyone know if bit 12 of the address register is used for
> anything?
 
MA12 causes hardware screen wrap-around. In MODE 0 if you set the screen
start address to &4000, then 3/4 of the way down the screen the CRTC gets
to &7FFF, and then gets to &8000 with MA12 set. When MA12 is set, an adder
circuit between the CRTC and the memory adds an offset to the base of
screen memory, so when the CRTC tries to access &8000 it accesses &3000.
 
MA12 has no effect if MA13 is set to select teletext, as the adder
circuitry only affects the addresses line buffers when MA13 is clear - ie,
not in Teletext mode.
 
-- 
J.G.Harston - jgh@...                - mdfs.net/User/JGH
Badly formed email is deleted unseen as spam
<< Previous Message Main Index Next Message >>
<< Previous Message in Thread This Month Next Message in Thread >>