Date   : Sun, 06 Nov 2005 15:58:36 +0100 (GMT)
From   : Johan Heuseveldt <johan@...>
Subject: Re: BBC using 3.5 high density format

Hi,

On Fri 04 Nov, Jonathan Graham Harston wrote:
> > Message-ID: <10511040849.ZM28453@...>
> Pete Turnbull <pete@...> wrote:
> > On Nov 4 2005,  0:20, Jonathan Graham Harston wrote:
> > 
> > > However, the BBC Master runs at 3MHz, so a 41-cycle NMI routine
> > 
> > Perhaps you're confusing the Master 128 with the Turbo or a 6502 Second
> > Processor.  The second processors do run at 3MHz, but the CPU and DRAM
> > clock in the Master is only 2MHz.
>  
> New Advanced User Guide, p30:
>  
> "1 instruction cycle=0.5us in a BBC model B, 0.33us in Master or
> 6520 2nd processor, 0.25us in a Master Turbo 2nd processor"

Checked, and yes, it's there; must be quite wrong though...
(an editing error?)

As the speed is heavily related with the RAM and screen RAM access
by the 6845, this doesn't make sense. 6502 and 6845 RAM access are
interleaved, and the maximum speed for the 6845 is 2MHz.

There is a 16MHz crystal for the system, and a frequency divider in
the Video ULA generating 8, 4, 2 and 1 MHz signal. All needed for
generating the CAS and RAS for the memory as well.
Only one 'strange' signal is derived from them, which is the 6MHz
for the teletext chip SAA 5050 (TR6 at pin 19)

A few other timings are coming from a second crystal of 17.73 MHz:
for video RGB and PAL output; nothing to do with RAM/6502 speed.

So, during 1 micro second, the memory is accessed twice by both the
6502 and 6845, so is actually 'running' at 4 MHz: every access has a
multiplexing of the address in a Row and Colomn part, gets addressed
at 8MHz: 4 ROW addresses and 4 COL addresses (during that 1 us).


(For mode 4-7 it is set to 1MHz by the 'Clock speed bit' (bit4) in
 the Video ULA control register, meaning the 6845 is addressing
 a location which got read twice by the addressing logic, as memory
 speed is not changed)


> but...
>  
> The Advanced Reference Manual for the BBC Master, p19:
>  
> "processing is done at 2MHz"
>  
> which is confirmed by the cuircuit diagram showing phi2 being fed
> from 2M on the Video processor.

Yep, so the above must be an error that hasn't been ironed out.

Please note there are many such errors in all those guides, probably
by copying each other, and/or overlooked during editing.
If you really get into it, they get spotted! Still, the info is of course
very valuable, and cross referencing these guides should resolve a lot of
them. Common sense c.q. rational thinking should do the rest! :-)

I can't without these guides! They are very precious to me!


greetings,
Johan

-- 
Johan Heuseveldt <johan@...              >
  aka  waarland

  The best place is a Riscy place
 
Friends: people who borrow my books and set wet glasses on them.