Date   : Tue, 02 Jan 2007 20:15:32 +0000
From   : splodge@... (Richard Gellman)
Subject: MOS ROM Structure

Hi,

One of my first projects for 2007 is to built the 8-bit IDE interface 
with a view to adding an IDE HD to my Master Turbo.  ROM space being 
tight, and socket 8 being used by ANFS for the Econet, my thought is to 
replace the built-in ADFS with the IDE-patched version (I don't plan to 
try and use an Acorn Winchester/SCSI hard drive as well).

Obviously this requires making a new 1Mbit ROM chip with a patched ADFS 
in it. So my questions are thus:

Is this a standard 128Kbyte ROM, or is there unusual/unexpected address 
decoding going on to map in the 16K OS ROM?
Does the chip use a standard pinout? My intention is to use a 27C1001 
(128k x 8) if compatible.
In what order are the ROMs laid out? I assume the paged ROMS are in the 
same order they appear in *ROMS, but where would the MOS ROM fit, I 
would hazard a guess at the end after ROM "15" (TERMINAL)?

As usual, I've Googled for info, but not come up with much (I suspect my 
choice of search terms are once again at fault), so if anyone can fill 
in the gaps in my knowledge I'd be very grateful :)

Cheers

-- Richard