Date   : Sun, 17 Feb 2008 20:46:18 +1100
From   : richard@... (Richard Wilson)
Subject: BBC FPGA Boots to BASIC... almost...

> I concur... The OS sets the PCR to have bit 0 clear, so the 
> interrupt occurs on negative edge of CA1. The 6845 sets CA1 
> high at start of vsync and puts it low at the end, with 
> position determined by 6845 R7 (specifies character row as I 
> recall, the vsync starting on line 0 of this row) and length 
> of pulse according to upper nybble of 6845 R3.
 
Oops, misread the register number on the Sys VIA, it gets set to 04 then 0E,
so it is the trailing edge.

Richard