Date   : Wed, 27 Feb 2008 08:24:08 +1100
From   : msmcdoug@... (Mark McDougall)
Subject: BBC FPGA Boots to BASIC... almost...

Jonathan Graham Harston wrote:

> Doh! Should be:
> 48 98 48 8A 48     PHA:TYA:PHA:TXA:PHA      :\ Save all registers
> BA BD 03 01        TSX:LDA &103,X           :\ Fetch A from stack
> C9 20 B0 02 A9 2A  CMP #32:BCS P%+4:LDA #42 :\ Change control code to '*'
> A0 00 91 D8        LDY #0:STA (&D8),Y       :\ Store into MODE 7 screen
> E6 D8 D0 02 E6 D9  INC &D8:BNE P%+4:INC &D9 :\ Increment &D8/9
> 68 AA 68 A8 68 60  PLA:TAX:PLA:TAY:PLA:RTS  :\ Pop all and return

Well, _that_ would've saved me some time hand-assembling! ;) I don't have 
any 6502 development environment handy so last night it was out with the 
trusty Rodney Zaks, then edit memory in hex mode and verify the disassembly 
in MESS! Now if it had been Z80, I probably could've assembled it in my head! :)

Thanks for the clarification - I thought the stack was at &100 but stupid me 
thought it grew downwards like Z80 - now I realise it would trash the 
zero-page. That with the LDA &103,A typo it didn't hit me - DOH!

> If the 6502 core implementation is not clears 'B' on a hardware
> IRQ, then when an IRQ happens after a BRK, then the 'B' is still
> set and the MOS will try to deal with it as a BRK. That would
> cause problems as the error handler would be repeatedly
> re-entered, pointing to arbitary machine code rather than an error
> block.

In light of the latest behaviour it's certainly looking like a real 
possibility, but I'm still leaning towards some unimplemented functionality 
looking like another interrupt source...

Thanks again!
Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"