Date : Tue, 26 Feb 2008 20:40:58 +0000
From : jgh@... (Jonathan Graham Harston)
Subject: BBC FPGA Boots to BASIC... almost...
Fragula wrote:
> >>TSX:LDA &103,A
> Shouldn't that be
> LDA &103,X
Doh! Should be:
48 98 48 8A 48 PHA:TYA:PHA:TXA:PHA :\ Save all registers
BA BD 03 01 TSX:LDA &103,X :\ Fetch A from stack
C9 20 B0 02 A9 2A CMP #32:BCS P%+4:LDA #42 :\ Change control code to '*'
A0 00 91 D8 LDY #0:STA (&D8),Y :\ Store into MODE 7 screen
E6 D8 D0 02 E6 D9 INC &D8:BNE P%+4:INC &D9 :\ Increment &D8/9
68 AA 68 A8 68 60 PLA:TAX:PLA:TAY:PLA:RTS :\ Pop all and return
Rob wrote:
> Do you need to initiaise &D8/D9 with &7C00 ...first?
The MOS does that by a direct jump to the VDU drivers on RESET
with LDA &28F:JSR &C300
Peter Coghlan wrote:
> Getting back to BRK, it has always been clear when the B flag is
> set but it I don't think I have ever found out when exactly it
> is cleared. I assume it gets cleared when there is an IRQ? If
Looking through documentation I cannot find anything explicit.
I've always assumed that a hardware IRQ clears 'B' and a software
IRQ (ie BRK) sets it, and nothing else effects it, other than PLP.
If the 6502 core implementation is not clears 'B' on a hardware
IRQ, then when an IRQ happens after a BRK, then the 'B' is still
set and the MOS will try to deal with it as a BRK. That would
cause problems as the error handler would be repeatedly
re-entered, pointing to arbitary machine code rather than an error
block.
You could try modifying the 6502 core so that BRK clears 'B' after
stacking it with 'B' set, viz:
PC=PC+2 (so PC points to the address of the BRK plus 2)
PSW = PSW OR &10 (setting B flag)
(SP) = PC DIV 256 (stack program counter)
SP = SP -1
(SP) = PC MOD 256
SP = SP -1
(SP) = PSW (stack flags)
SP = SP -1
PSW = PSW OR &04 (setting I flag, disabling IRQs)
PSW = PSW AND &EF (clear B flag - additional)
--
J.G.Harston - jgh@... - mdfs.net/User/JGH
Jet Set Willy Resources - http://mdfs.net/Software/JSW