<< Previous Message Main Index Next Message >>
<< Previous Message in Thread This Month Next Message in Thread >>
Date   : Wed, 19 Mar 2008 00:20:58 +0100 (GMT)
From   : johan@... (Johan Heuseveldt)
Subject: New 6809 TUBE, was: TUBE chip,

Hi Pete,

Sorry, I seemed to be a bit vague in my descriptions...

On Tue 18 Mar, Pete Turnbull wrote:
> On 18/03/2008 20:12, Johan Heuseveldt wrote:
> 
> > I'm not sure what family of IC's I can use HC or HCT. Normally I would
> > expect HCT, as the NMOS 6809 is TTL compatible, TTL only. Not sure how to
> > interpret that. But reading some details about these HC/HCT families, the
> > difference is certainly not as much as with the CMOS 4000 family.
> 
> Basically, the upper/lower thresholds on HC inputs are symmetrical, like 
> most CMOS (eg 4000-series) while the thresholds on HCT match normal 
> TTL/LSTTL.

Ah, I think I recognized that from the descriptions read. More dificult is to
crasp what will happen if going from HC to HCT and from HCT to HC. Will a '1'
be understood as a '1', and '0' similar. With CMOS 4000 and 74xx(x) this
wasn't so!

> > I need two seperate latches/registers for bank switching, both two bits
> > in size. An 75 is available in both HC and HCT. But being a transparent
> > latch, it needs an active high signal, while it is better to use a active
> > low signal. 
> 
> Um, perhaps you've just not written that the way I'd expect to hear it, 
> but it latches when the enable is low; the output tracks the input when 
> the enable is high.

That's what I meant. The 'window' to open the latch, so that outputs follow
the input, is high. At the moment the control signal goes low, the data is
latched. Indeed what I meant and said by you. Sorry for being unclear.

You could say that activating this process is going to the level of that
window, which is high. This means the normal state, being INactive or
DEasserted is low, which is the opposit compared to positive edge triggered
latches. Doing that on the trailing edge, the signal stays at high level.

> > When inactive, a high signal is very much unsensitive for noise.
> 
> I'm not sure what you mean here, and the input impedance of HC or HCT is 
> high enough that there's little difference in sensitivity to high versus 
> low.  Besides, so long as the input is connected to something active, it 
> won't matter.

OK. Clear enough.
Then there's only the level of the signal itself which is a wire of some
length, and can be receptive to noise. High signals are less susceptable for
that than low signals. That's my understanding.

> > A newer 77 is only available in HC, but has the same signal level problem.
> 
> Yes, it's a '75 without the not-Q outputs which are available on the '75.
> 
> > A 175 is usable, although the double latch outputs are not necessary. But
> > it does use a more normal low active pulse, so the positive edge is used
> > to clock the data into the latches, keeping the inactive state of the signal
> > level to high, which is prefered. 
> 
> Yes, it's a D-type flip-flop, not a transparent latch like the 75/77. 
> It's edge-triggered, which latches are not.
> 
> > Another issue is the actual availability of all of them. In the end it
> > could be that only a 174 is the one that could actually be obtained, apart
> > from the more usual 8 bits variants.
> 
> Again, the 174 is a D-type flip-flop, not a latch.  Also 
> positive-edge-triggered, like the 175; in fact the 175 is just a quad 
> version of the (hex) 174.

Indeed I was inaccurate here. Sorry.
But some documentation says latches in two versions: transparent and edge
triggered. The data sheet book from Elektor is consistent with you,
differentiating between latches and FlipFlops. I'll be more precise in
future! :-)

> All the latches/flip-flops in the chips you've listed have a common 
> clock, so you can't clock two bits in any of them without clocking the 
> other bits at the same time. 

No, the 75, 77 and 375 have /two/ clocks: one clock line per two bits.
That's why I consider these devices, but wasn't content with the opposit
signal level of the active/inactive states, and also notice the absence of
a HCT variant. 

> You wrote that you need two 2-bit latches;  if they need to be capable of
> being clocked separately, you need two  chips anyway.  If so, why not use a
> pair of 74HCT74s?  Each is a dual  D-type flip-flop, and they're readily
> available and cheap.

It increases chip count! :-)
And then I have seperate clocks for each bit, as well as resets and presets.

There will be an electrical issue then, for which I'm very uncertain. If I
want to reset the four bits, also 4 /extra/ resets are connected to the RES
line. I'm not sure if the 122 can sink that current; there are pull-up
resistors everywhere!

OK, in the end I solved that in software without using explicit code.
It happens during the copying process of the ROM to RAM.
Just an extra Product Term in a GAL.

> HCT173 also exists, it's a tri-state quad D-type.

It's rather big for 4 bits, having a few extra signals which aren't
necessary for me.

> Or cheat and use an  HCT161: you can set it up so it does a parallel 4-bit
> load on the clock  transition, without counting (Acorn used an LS163 to do
> this in the  Beeb's ROM select circuit) -- if either of the two count
> enables are  low, counting is inhibited, and the parallel inputs are
> latched and  transferred to the outputs when the Parallel Enable
> transitions from  high to low.

Ah, I /do/ know that , and still hadn't thought about that. :-(

> Or just use half of an HCT273 (flip-flops), HCT373 (latches), HCT374 
> (flip-flops), HCT573 (latches), or HCT374 (flip-flops).  All common.

A few bits to much, and a bigger size of the chip. Don't know yet if that
will be an issue when wiring the back of the VERO board.

I probably put the two 2-bits registers in one chip with a single clock.
Software overhead is minimal I think. The third register will have its own
clock and seperate chip. A LED can be added for software testing purposes.

> > I think the GALs are also fully TTL compatible, 
> 
> Yes.
> 
> > so considerations are:
> >  * the proper IC family is possibly HCT anyway?
> 
> Yes.
> 
> >  * it's probably not good to mix HC and HCT?
> 
> No, the thresholds are different, but it will usually work.

Thanks for the confirmation. Now I can make up my mind on this.
It depends a bit on what is available from the shop.
But definitely HCT.

Thanks Pete, for your input. Much appreciated.


Johan

-- 
Johan Heuseveldt <johan@...              >
  aka  waarland

  The best place is a Riscy place
 
All bicycles weigh 50 pounds. A 30 pound bicycle needs
a 20 pound lock. A 40 pound bicycle needs a 10 pound
lock. A 50 pound bicycle doesn't need a lock.
<< Previous Message Main Index Next Message >>
<< Previous Message in Thread This Month Next Message in Thread >>