Date : Wed, 19 Mar 2008 01:01:59 +0000
From : pete@... (Pete Turnbull)
Subject: New 6809 TUBE, was: TUBE chip,
On 18/03/2008 23:20, Johan Heuseveldt wrote:
> On Tue 18 Mar, Pete Turnbull wrote:
>> On 18/03/2008 20:12, Johan Heuseveldt wrote:
> Basically, the upper/lower thresholds on HC inputs are symmetrical,
> like
>> most CMOS (eg 4000-series) while the thresholds on HCT match normal
>> TTL/LSTTL.
>
> Ah, I think I recognized that from the descriptions read. More
> dificult is to crasp what will happen if going from HC to HCT and
> from HCT to HC. Will a '1' be understood as a '1', and '0' similar.
Yes, because the outputs of HC and HCT both swing almost rail-to-rail,
both will produce a logic '1' high enough to be recognised as such by
any logic family; similarly a '0' is low enough for anything.
> With CMOS 4000 and 74xx(x) this wasn't so!
Indeed -- because although a TTL logic '0' is low enough for CMOS to see
it as such, a TTL '1' isn't guaranteed to be high enough to be seen as
such by a CMOS input. The standard solution is to add a pullup
resistor. Going the other way, most ordinary CMOS 4000 series doesn't
have enough drive capability to pull a TTL input low enough to guarantee
a '0' (high is fine for a logic '1'). The fix is to use a buffer.
> That's what I meant. The 'window' to open the latch, so that outputs
> follow the input, is high. At the moment the control signal goes low,
> the data is latched. Indeed what I meant and said by you. Sorry for
> being unclear.
> You could say that activating this process is going to the level of
> that window, which is high. This means the normal state, being
> INactive or DEasserted is low, which is the opposit compared to
> positive edge triggered latches. Doing that on the trailing edge, the
> signal stays at high level.
IME the latching action is usually considered the active state, but some
places teach the reverse, ie that the outputs-follow-inputs state is the
active one.
>>> When inactive, a high signal is very much unsensitive for noise.
>> I'm not sure what you mean here, and the input impedance of HC or
>> HCT is high enough that there's little difference in sensitivity to
>> high versus low. Besides, so long as the input is connected to
>> something active, it won't matter.
>
> OK. Clear enough. Then there's only the level of the signal itself
> which is a wire of some length, and can be receptive to noise. High
> signals are less susceptable for that than low signals. That's my
> understanding.
OK, the signal is on a wire of some length. That wire can have a
current induced in it by inductance or capacitance, and such currents
are noise. Unless the wire is long, the external field is strong, or
the impedances of the input and the driver are high, it's not a problem.
It's never generally a problem with signals which are actively driven,
unless you have long cables or some lengthy parallel bus, especially
since with HC and HCT there's quite a lot of drive capability. I don't
know where you get the idea that a logic high is less susceptible than a
logic low, because with HC and HCT there's virtually no difference.
With TTL it's less clear; it takes more current to pull down an isolated
TTL input than it does to raise it, so you might think it's harder to
pull down a high than pull up a low, but in fact TTL outputs are
designed to do exactly that (pull down). It's easier to override a high
TTL output by pulling it down than to do the reverse. If you left an
input floating, that would be a different story; TTL inputs tend to
float high, but you should never ever rely on that, and always tie it to
an output or provide an appropriate pullup or pulldown, on any unused or
floating input with any logic family.
In practice, bus systems and the like, designed around TTL and similar
logic, often use high as the quiescent state for quite a different
reason than noise immunity of one state over the other. It's simply
that it takes less current in a pullup resistor to keep a supposedly
high signal at logic '1', and it's much easier for a TTL or similar
driver to pull down a line to a '0' in this case than to pull up a line
that has a pull-down resistor (remember TTL, LS TTL et al are much
better at pulling things down than pulling them up). This reasoning
doesn't apply in the case of device families that have essentially
symmetrical output stages, like HC and HCT.
> Indeed I was inaccurate here. Sorry. But some documentation says
> latches in two versions: transparent and edge triggered. The data
> sheet book from Elektor is consistent with you, differentiating
> between latches and FlipFlops. I'll be more precise in future! :-)
The are lots of different kinds of flip-flops; the ones we're describing
here are D-type, but JK, SR, T, B, and other types also exist. All use
cross-coupled gates in their construction, but transparent latches
generally don't (though they can). So generally they're considered to
be slightly different things, though of course they have several
applications in common.
> No, the 75, 77 and 375 have /two/ clocks: one clock line per two
> bits.
Ah yes, I'd forgotten that. You are indeed correct there (note to self:
check data book before hitting keyboard).
> There will be an electrical issue then, for which I'm very uncertain.
> If I want to reset the four bits, also 4 /extra/ resets are
> connected to the RES line. I'm not sure if the 122 can sink that
> current; there are pull-up resistors everywhere!
HC(T) inputs are fairly high impedance; I'd not worry about the extra
load unless things are marginal already.
--
Pete Peter Turnbull
Network Manager
University of York