Date   : Mon, 24 Mar 2008 16:02:13 +0100 (GMT)
From   : johan@... (Johan Heuseveldt)
Subject: New 6809 TUBE

Hi Jonathan,

On Sat 22 Mar, Jonathan Graham Harston wrote:
> Johan Heuseveldt wrote:

> I've been away for a few days, so I'm entering this thread a bit
> late...
>  
> > Sometimes the several design options don't allow for two seperate bank
> > switch registers, as I'm running out of GAL in- and outputs. In fact I
> > also need three other bits for the
>  
> Eurghhh!!! I *hate* designes that use PALs and GALs. You just have
> an annonymouse black box in the middle of the design with no idea
> what it does and no possibility of reproducing it.

Nothing black I suppose. A GAL can be protected, but I'm not going to use
that, so can be read back. More than that, the design will be published on
my site eventually, complete with GAL design in boolean expressions.
No black magic then! :-)

> Is your design
> really so complicated that you can't implement it with a couple of
> logic ICs? If it is that complex, it's too complex.

Do you realy mean that?
My "experience" is different. On paper yes indeed, as I have done for many
years. But gates come together in single chips, and it is hard to put the
chip efficiently on a PCB for a particular gate combination, as it also
means it can be very inefficient for the other gates in the IC. More chips
definitely makes this more complex. Other problems are something like the
need of 7 invertors, 6 available per package. Even trying out a PCB layout
on paper just to get the feeling how the wiring turns out for the
interconnection of IC's, can show the problems involved, while the actual
design on paper looks so good! In this case this is relevant, as the VERO
board will be wired manually. I suppose it's not a real issue with EDA
software.

> A quick bit of scribbling (not knowing exactly what you're trying
> to implement, and what your bank sizes are) suggests a 8-in NAND
> and two halves of a 2-to-4 decoder for I/O selection, an XOR for
> vector selection, and the rest of the XOR gates for a couple of
> inverters.

I started like that.
Soon I saw other possibilities and changed to the black box principle. With
only a few chips for the glue logic, it is easy to wire up the connections,
leaving the intelligent bit described in boolean logic inside.

Atm I'm busy drawing more usefull schematics, so I can put them on the
Internet. Till then it is rather complicated to express all the design
philosophy in words only. So, I'll leave that until then.

This week I start looking for the actual chips available. Then I can finilize
the design.


Johan

-- 
Johan Heuseveldt <johan@...              >
  aka  waarland

  The best place is a Riscy place
 
Nobody ever ruined their eyesight by looking
at the bright side of something.