Date   : Mon, 24 Mar 2008 15:54:03 +0000
From   : jgh@... (Jonathan Graham Harston)
Subject: New 6809 TUBE

jgh@... (Jonathan Graham Harston) (Jonathan Graham Harston)
wrote:
> If you clarify a bit what memory banking system you're aiming
> for and what hardware I/O you're looking at (obviously, Tube)
> I can scribble something together.
 
A bit more rummaging through documents and a bit more scribbling.
Most 6809 systems have memory banking in chunks of 4K, more or
less what http://mdfs.net/Info/Comp/Z80/Circuits/1MbMem.gif
implements.
 
(Sidebar: Each bank of memory at logical address &X*** is mapped
to physical address &YY***. This allows any 4K chunk of physical
memory to be mapped to appear as any 4K chunk of logical memory.
Think of the BBC sideways ROM system, but with 4K banks, and any
bank can be paged in at any 4K boundary.)
 
With no MMU you can put together a system with half a '139 for I/O
decoding, half a '139 for BA/BS vector fetch decoding, an XOR for
vector fetch address translation, the other three XORs used as
NOTs, and a 13-in NAND for I/O address selection, three ICs.
 
A15-A6 selecting I/O gives I/O paged in at &FEC0-&FEFF, subdecoded
into 16-byte chunks, FECx, FEDx, FEEx, FEFx which could feed four
I/O devices directly. Tube, VIA, MMU, Other? 'Other' could feed
back to select RAM if you do want vectors at &FEFx.
 
Adding MMU, based on 1MbMem.gif above, you could use a '157 4 time
2-to-1 selector, '89 16*8bit RAM and '245 8bit buffer.
 
I've put a few notes at http://mdfs.net/Info/Comp/6809
 
> Something that may influence the design is if you use BA/BS to
> toggle A9 instead of A8, so putting the hardware vectors at
> &FDFx instead of &FEFx, then it makes decoding for hardware
 
Or toggle A7 to put vectors at &FF7x.
 
-- 
J.G.Harston - jgh@...                - mdfs.net/User/JGH
The most perfect world is an imperfect world as the imperfections
give people a reason to strive to change it.