Date   : Thu, 24 Jul 2008 16:45:09 +0100
From   : Charlie.Robson@... (Charlie.Robson@...)
Subject: EEPROM writing in SW rom bank?

Peter Coghlan <PCOGHLAN@...> wrote on 24/07/2008 16:13:48:

> I looked into doing this for (part of) an AT28C256 and found (for 
reasons
> that I have now forgotten) that it was not straightforward.
> 
> It could have been something like OE being in the wrong state or CE not
> asserted for long enough, the address bus not being stable for long
> enough or something else entirely.
> 
> I decided that the way to proceed was to modify my eprom programmer to
> do the writing, and then never got around to finishing the job...
> 
> As far as I recall, the data sheet for the AT28C256 said it could be
> programmed one byte at a time or in "page mode" (64 bytes at a time).
> Selection of page mode was determined by writing the subsequent bytes
> quickly enough after the first one. If you weren't quick enough, it
> went off in a huff to program the first byte for a considerable time
> before becoming ready to accept another byte. This would probably
> manifest as the first byte getting written, followed by a big gap
> followed by a byte written much further along etc etc. Of course the
> 28c64 could be completely different...

I think you're right there peter. The required confluence of signals
looks pretty tight and I'm of the opinion that it's highly unlikely
that they look anything like they ought to. Control over this would
be impossible so I think that, given that I'm confident in the code and
protocol being applied, it's game over for the eeprom programming :)

I'm off to try and track down a '299 shift register to build the easy
peasy parallel programmer that mr. google just found for me!



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