Date   : Mon, 05 Nov 2012 08:01:17 +0000
From   : jgh@... (J.G.Harston)
Subject: 6502 timing and zero-page instructions

Jules Richardson wrote:
> Aha, silly question related to the above about the program counter, 
> but
> presumably given the PC pre-increment that the 6502 seems to do on a 
> memory
> fetch, the interrupt and reset vectors stored at 0xfffc and 0xfffe 
> have to
> be 1 byte less than their true location?

The IRQ, RST and NMI vectors are the actual destination address, they 
are
effectively the address field of a JSR or JMP instruction (except that
P and PC is pushed, whereas JSR pushes PC-1). For example, the contents 
of
NMIV is &0D00 and NMIs vector to &0D00.

-- 
J.G.Harston - jgh@...      - mdfs.net