Date   : Mon, 05 Nov 2012 10:41:37 +0000
From   : percy.p.person@... (Ed Spittles)
Subject: 6502 timing and zero-page instructions

Hi Jules,
   The PC is generally incremented: the other possible actions are to leave
it alone, and to reload it.  The logic for this is quite complex - I wrote
something about it here:
http://visual6502.org/wiki/index.php?title=6502_increment_PC_control
but the conclusion is that your first tabulation is right: the PC is
incremented for each operand.  The 6502 has to make a hasty decision not to
increment the PC when it fetches an opcode which has no operand: the PC was
already incremented, but that's fine because it's correct to be used to
fetch the next instruction - unless it's about to be reloaded.

   The 'PC' value shown by the visual6502 simulation can be taken as a true
representation, since the simulation is operating at the transistor level
(modelling the transistors as switches) and contains no 6502-specific
information other than the presentation.  (As each bit is a master-slave
circuit, there are in a sense two PC values but I don't think we need that
level of detail[1])

   In the URL I gave, I set the reset vector to 0 using &r=0, but the
memory model already has 0 in all the vectors so that was unnecessary. The
simulator actually runs for several steps before time 0, to complete the
reset sequence, so the best way to see what happens at reset is to cause a
reset at a later time:
http://www.visual6502.org/JSSim/expert.html?graphics=f&a=fffc&d=3412&a=0&d=a901a002a203&a=1234&d=4c0200&logmore=dpc36_~IPC,State,res&reset0=4&reset1=14&steps=40
(The simulation traces the PC-increment control, and shows of course that
JGH is correct)

   I wrote up some help on the URL syntax here:
http://visual6502.org/wiki/index.php?title=JssimUserHelp#URL_interface

Cheers
Ed

[1] But see
http://www.visual6502.org/JSSim/expert.html?graphics=f&a=0&d=ea18a0ffeab0ff90f7ea&logmore=dpc36_~IPC,pcl0,526,State&steps=40
for an illustration. The signals of interest are:
dpc36_~IPC  -- PC increment control, negative sense
pcl0 -- LSB of the PC
526 -- the other half of the master-slave pair which holds pcl0